A new heuristic for N-dimensional nearest neighbor realization of a quantum circuit by Kole A., Datta K. , Sengupta I. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2017)
A heuristic for linear nearest neighbor realization of quantum circuits by SWAP gate insertion using N-gate lookahead by Kole A., Datta K. , Sengupta I. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 62-72 (2016)
In-field test for permanent faults in FIFO buffers of NoC routers by Ghoshal B., Manna K. , Chattopadhyay S. , Sengupta I. IEEE Transactions on VLSI Systems 24 393-397 (2016)
A post-synthesis optimization technique for reversible circuits exploiting negative control lines by Datta K., Sengupta I. , Rahaman H. IEEE Transactions on Computers 64 1208-1214 (2015)
Scan chain masking for diagnosis of multiple chain failures in a space compaction environment by Kundu S., Chattopadhyay S. , Sengupta I. , Kapur R. IEEE Transactions on VLSI Systems 23 1185-1195 (2015)
An approach to reversible logic synthesis using input and output permutations by Datta K., Sengupta I. , Rahaman H. , Drechsler R. Transactions on Computational Science 24 92-110 (2014)
An improved reversible circuit synthesis approach using clustering of ESOP cubes by Datta K., Rathi G. , Sengupta I. , Rahaman H. ACM Journal on Emerging Technologies in Computing (JETC) 11 1-16 (2014)
Framework for multiple-fault diagnosis based on multiple fault simulation using particle swarm optimization by Kundu S., Jha A. , Chattopadhyay S. , Sengupta I. , Kapur R. IEEE Transactions on VLSI Systems 22 696-700 (2014)
Construction of RSBFs with improved cryptographic properties to resist differential fault attack on grain family of stream ciphers by Mazumdar B., Mukhopadhyay D. , Sengupta I. Cryptography and Communications 7 35-69 (2015)
Integrated Through Silicon Via Placement and Application Mapping for 3D Mesh Based NoC Design by Manna K., Swami S. , Chattopadhyay S. , Sengupta I. ACM Transactions on Embedded Computing Systems - (Accepted/In-Press)
RTOS Validation and Development Support Hindustan Aeronautics Limited, MCSRDC Division
Synopsys CAD Laboratory Project Phase II Synopsys Inc.
Security Concerns in a Scan Compression Environment for DFTMAX Ultra Synopsys Inc.
Area of Research: Hardware Security
Area of Research: Memristor based logic design