Indian Institute of Technology Kharagpur |

Patent

Transistor level defect coverage and defect simulation Bhattacharyya M., Sanyal S. , Patra A. , Dasgupta P. By - (2023)

Conferences

Domain Adaptation of Reinforcement Learning Agents based on Network Service Proximity Dey K., Perepu S. K., Dasgupta P. , Das A. By Global Communications Conference 1-9 (2023)
Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits Sanyal S., Hazra A. , Dasgupta P. , Morrison S. , Surendran S. , Balasubramanian L. By 26th Design, Automation and Test in Europe Conference (DATE) 1-6 (2023)
Domain Adaptation of Reinforcement Learning Agents based on Network Service Proximity Dey K., Perepu S. K., Dasgupta P. , Das A. By Global Communications Conference 1-9 (2023)
Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits Sanyal S., Hazra A. , Dasgupta P. , Morrison S. , Surendran S. , Balasubramanian L. By 26th Design, Automation and Test in Europe Conference (DATE) 1-6 (2023)
SymDNN: Simple & Effective Adversarial Robustness for Embedded Systems Dey S., Dasgupta P., Chakrabarti P.P. By IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops 2022-June 3598-3608 (2022)
SymDNN: Simple & Effective Adversarial Robustness for Embedded Systems Dey S., Dasgupta P., Chakrabarti P.P. By IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops 2022-June 3598-3608 (2022)
Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions Chakraborty A., Sanyal S., Dasgupta P., Hazra A., Morrison S., Surendran S., Balasubramanian L. By Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 132-137 (2022)
Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions Chakraborty A., Sanyal S. , Dasgupta P. , Hazra A. , Morrison S. , Surendran S. , Balasubramanian L. By 35th International Conference on VLSI Design (VLSID) 132-137 (2022)
Refinement Of Reinforcement Learning Algorithms Guided By Counterexamples Gangopadhyay B., Vishnoi S., Dasgupta P. By WINTECHCON 2022 - 2022 IEEE Women in Technology Conference - (2022)
Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions Chakraborty A., Sanyal S., Dasgupta P., Hazra A., Morrison S., Surendran S., Balasubramanian L. By Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 132-137 (2022)
Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions Chakraborty A., Sanyal S. , Dasgupta P. , Hazra A. , Morrison S. , Surendran S. , Balasubramanian L. By 35th International Conference on VLSI Design (VLSID) 132-137 (2022)
Refinement Of Reinforcement Learning Algorithms Guided By Counterexamples Gangopadhyay B., Vishnoi S., Dasgupta P. By WINTECHCON 2022 - 2022 IEEE Women in Technology Conference - (2022)
Glitch and Level Detection Algorithms for Analog Mixed-Signal Verification Coverage Management (Poster) Sanyal S., Hazra A. , Dasgupta P. , Morisson S. , Surendran S. , Balasubramanian L. By 58th Design Automation Conference (DAC) - (2021)
Glitch and Level Detection Algorithms for Analog Mixed-Signal Verification Coverage Management (Poster) Sanyal S., Hazra A. , Dasgupta P. , Morisson S. , Surendran S. , Balasubramanian L. By 58th Design Automation Conference (DAC) - (2021)
ML-assisted Real Time Congestion Mitigation under Supply-side Uncertainties Verma P., Dasgupta P. , Chakraborty C. By Innovative Smart Grid Technologies Conference Asia (ISGT Asia 2021) - (2021)
Counterexample Guided RL Policy Refinement using Bayesian Optimization Gangopadhyay B., Dasgupta P. By NeurIPS 22783-22794 (2021)
ML-assisted Real Time Congestion Mitigation under Supply-side Uncertainties Verma P., Dasgupta P. , Chakraborty C. By Innovative Smart Grid Technologies Conference Asia (ISGT Asia 2021) - (2021)
Counterexample Guided RL Policy Refinement using Bayesian Optimization Gangopadhyay B., Dasgupta P. By NeurIPS 22783-22794 (2021)
An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors Mandal S., Gaurkar K., Dasgupta P., Hazra A. By Proceedings of the IEEE International Conference on VLSI Design 2021-February 181-186 (2021)
An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors Mandal S., Gaurkar K., Dasgupta P., Hazra A. By Proceedings of the IEEE International Conference on VLSI Design 2021-February 181-186 (2021)
The Notion of Cross Coverage in AMS Design Verification Sanyal S., Hazra A. , Dasgupta P. , Morrison S. , Surendran S. , Balasubramanian L. By Asia and South Pacific Design Automation Conference - (2020)
The Notion of Cross Coverage in AMS Design Verification Sanyal S., Hazra A. , Dasgupta P. , Morrison S. , Surendran S. , Balasubramanian L. By Asia and South Pacific Design Automation Conference - (2020)
Safety augmentation in decision trees Dey S., Dasgupta P., Gangopadhyay B. By CEUR Workshop Proceedings 2640 - (2020)
Fault vulnerability ranking of transistors in analog integrated circuits using AC analysis Garapati S.P.P.K., Sanyal S., Patra A., Dasgupta P., Bhattacharya M. By 2020 IEEE International Test Conference India, ITC India 2020 - (2020)
CoveRT: A Coverage Reporting Tool for AMS Designs Sanyal S., Hazra A. , Dasgupta P. , Morrison S. , Surendran S. , Balasubramanian L. By International Conference on VLSI Design - (2020)
Safety augmentation in decision trees Dey S., Dasgupta P., Gangopadhyay B. By CEUR Workshop Proceedings 2640 - (2020)
Fault vulnerability ranking of transistors in analog integrated circuits using AC analysis Garapati S.P.P.K., Sanyal S., Patra A., Dasgupta P., Bhattacharya M. By 2020 IEEE International Test Conference India, ITC India 2020 - (2020)
CoveRT: A Coverage Reporting Tool for AMS Designs Sanyal S., Hazra A. , Dasgupta P. , Morrison S. , Surendran S. , Balasubramanian L. By International Conference on VLSI Design - (2020)
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis Sanyal S., Garapati S. , Patra A. , Dasgupta P. , Bhattacharya M. By Great Lakes Symposium on VLSI - (2019)
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis Sanyal S., Garapati S. , Patra A. , Dasgupta P. , Bhattacharya M. By Great Lakes Symposium on VLSI - (2019)
Synthesizing Performance-aware (m,k)-firm Control Execution Patterns under Dropped Samples Ghosh S., Dey S. , Dasgupta P. By VLSI Design - (2019)
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits Sanyal S., Patra A. , Dasgupta P. , Bhattacharya M. By Asian Test Symposium - (2019)
Identification of Test Cases for Automated Driving Systems Using Bayesian Optimization Gangopadhyay B., Khastgir S. , Dey S. , Dasgupta P. , Montana G. , Jennings P. By IEEE Intelligent Transportation Systems Conference - (2019)
ALAFA: Automatic Leakage Assessment for Fault Attack Countermeasures Saha S., Kumar S. N., Patranabis S. , Mukhopadhyay D. , Dasgupta P. By Design Automation Conference - (2019)
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits Sanyal S., Patra A. , Dasgupta P. , Bhattacharya M. By Asian Test Symposium - (2019)
Synthesizing Performance-aware (m,k)-firm Control Execution Patterns under Dropped Samples Ghosh S., Dey S. , Dasgupta P. By VLSI Design - (2019)
Identification of Test Cases for Automated Driving Systems Using Bayesian Optimization Gangopadhyay B., Khastgir S. , Dey S. , Dasgupta P. , Montana G. , Jennings P. By IEEE Intelligent Transportation Systems Conference - (2019)
ALAFA: Automatic Leakage Assessment for Fault Attack Countermeasures Saha S., Kumar S. N., Patranabis S. , Mukhopadhyay D. , Dasgupta P. By Design Automation Conference - (2019)
AMS-Miner: Mining AMS Assertions using Interval Arithmetic Bruto Da Costa A. A., Dharade S. , Mandal S. , Dasgupta P. By VLSI Design 404-409 (2018)
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components Mandal S., Hazra A. , Dasgupta P. , Mohan C. R. By VLSI Design 37-42 (2018)
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components Mandal S., Hazra A. , Dasgupta P. , Mohan C. R. By VLSI Design 37-42 (2018)
Breaking Redundancy-Based Countermeasures with Random Faults and Power Side Channel Saha S., Jap D. , Breier J. , Bhasin S. , Mukhopadhyay D. , Dasgupta P. By IEEE Int. Workshop Fault Diagnosis and Tolerance in Cryptography 15-22 (2018)
Solar Irradiance Prediction from Historical Trends using Deep Neural Networks Mukherjee A., Ain A. , Dasgupta P. By IEEE International Conference on Smart Energy Grid Engineering 356-361 (2018)
A Machine Learning Approach for Choosing Component Level Conditions for Prognostics of AMS Systems Sanyal S., Ain A. , Dasgupta P. By ISDCS - (2018)
Breaking Redundancy-Based Countermeasures with Random Faults and Power Side Channel Saha S., Jap D. , Breier J. , Bhasin S. , Mukhopadhyay D. , Dasgupta P. By IEEE Int. Workshop Fault Diagnosis and Tolerance in Cryptography 15-22 (2018)
AMS-Miner: Mining AMS Assertions using Interval Arithmetic Bruto Da Costa A. A., Dharade S. , Mandal S. , Dasgupta P. By VLSI Design 404-409 (2018)
Solar Irradiance Prediction from Historical Trends using Deep Neural Networks Mukherjee A., Ain A. , Dasgupta P. By IEEE International Conference on Smart Energy Grid Engineering 356-361 (2018)
Feature Based Coverage Analysis of AMS Circuits Ain A., Mambakam A. , Dasgupta P. By VLSID 2018 37-42 (2018)
A Machine Learning Approach for Choosing Component Level Conditions for Prognostics of AMS Systems Sanyal S., Ain A. , Dasgupta P. By ISDCS - (2018)
Feature Based Coverage Analysis of AMS Circuits Ain A., Mambakam A. , Dasgupta P. By VLSID 2018 37-42 (2018)
Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs Ain A., Mambakam A. , Dasgupta P. , Mukhopadhyay S. By VLSI Design 245-250 (2017)
ForFET: A Formal Feature Evaluation Tool for Hybrid Systems (Tool Paper) Bruto Da Costa A. A., Dasgupta P. By ATVA - (2017)
ForFET: A Formal Feature Evaluation Tool for Hybrid Systems (Tool Paper) Bruto Da Costa A. A., Dasgupta P. By ATVA - (2017)
Formal Verification of Power Management Logic with Mixed-Signal Mondal S., Bruto Da Costa A. A., Hazra A. , Dasgupta P. , Naware B. , Mohan C. R., Basu S. By VLSI Design 239-244 (2017)
Formal Verification of Power Management Logic with Mixed-Signal Mondal S., Bruto Da Costa A. A., Hazra A. , Dasgupta P. , Naware B. , Mohan C. R., Basu S. By VLSI Design 239-244 (2017)
Generating AMS Behavioral Models with Formal Guarantees on Feature Accuracy Bruto Da Costa A. A., Dasgupta P. By VLSI Design 233-238 (2017)
Generating AMS Behavioral Models with Formal Guarantees on Feature Accuracy Bruto Da Costa A. A., Dasgupta P. By VLSI Design 233-238 (2017)
A Framework for Automated Feature Based Mixed-Signal Equivalence Checking Ain A., Sanyal S. , Dasgupta P. By VLSI Design and Test - (2017)
An Automated Framework for Exploitable Fault Identification in Block Ciphers A Data Mining Approach Saha S., Kumar U. , Mukhopadhyay D. , Dasgupta P. By 6th International Workshop on Security Proofs for Embedded Systems (PROOFS) - (2017)
A Framework for Automated Feature Based Mixed-Signal Equivalence Checking Ain A., Sanyal S. , Dasgupta P. By VLSI Design and Test - (2017)
Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs Ain A., Mambakam A. , Dasgupta P. , Mukhopadhyay S. By VLSI Design 245-250 (2017)
An Automated Framework for Exploitable Fault Identification in Block Ciphers A Data Mining Approach Saha S., Kumar U. , Mukhopadhyay D. , Dasgupta P. By 6th International Workshop on Security Proofs for Embedded Systems (PROOFS) - (2017)
A Robust Non-Parametric and Filtering Based Approach for Glottal Closure Instant Detection Rengaswamy P., M G. R., Rao K. S., Dasgupta P. By INTERSPEECH 2016, ISCA - (2016)
Formal Feature Analysis of Hybrid Automata Bruto Da Costa A. A., Dasgupta P. By MEMOCODE - (2016)
Formal Verification of Movement Authorities in Automatic Train Control Systems Ghosh S., Dasgupta P. , Mandal C. , Katiyar A. By IET International Conference on Railway Engineering - (2016)
Formal Feature Analysis of Hybrid Automata Bruto Da Costa A. A., Dasgupta P. By MEMOCODE - (2016)
Formal Verification of Movement Authorities in Automatic Train Control Systems Ghosh S., Dasgupta P. , Mandal C. , Katiyar A. By IET International Conference on Railway Engineering - (2016)
Scheduling of Controllers' Update-rates for Residual Bandwidth Utilization Zamani M., Dey S. , Mohamed S. , Dasgupta P. , Jr. M. M. By FORMATS - (2016)
Scheduling of Controllers' Update-rates for Residual Bandwidth Utilization Zamani M., Dey S. , Mohamed S. , Dasgupta P. , Jr. M. M. By FORMATS - (2016)
A Robust Non-Parametric and Filtering Based Approach for Glottal Closure Instant Detection Rengaswamy P., M G. R., Rao K. S., Dasgupta P. By INTERSPEECH 2016, ISCA - (2016)
A new approach for minimal environment construction for modular property verification Dutta S., Chattopadhyay S. , Banerjee A. , Dasgupta P. By Asian Test Symposium - (2015)
Formal Methods for Pattern Based Reliability Analysis in Embedded Systems Ghosh S., Dasgupta P. By VLSI Design - (2015)
Raga identification based on Normalized Note Histogram features Pradeep R., Dhara P. , Rao K. , Dasgupta P. By ICACCI 1491-1496 (2015)
Formal Methods for Pattern Based Reliability Analysis in Embedded Systems Ghosh S., Dasgupta P. By VLSI Design - (2015)
Monitoring AMS Simulation: From Assertions to Features Ain A., Dasgupta P. By VLSI Design - (2015)
Adaptive Sharing of Sampling Rates among Software Based Controllers Raha R., Dey S. , Dasgupta P. By Multiconference on Systems and Control (MSC) - (2015)
A new approach for minimal environment construction for modular property verification Dutta S., Chattopadhyay S. , Banerjee A. , Dasgupta P. By Asian Test Symposium - (2015)
Raga identification based on Normalized Note Histogram features Pradeep R., Dhara P. , Rao K. , Dasgupta P. By ICACCI 1491-1496 (2015)
Monitoring AMS Simulation: From Assertions to Features Ain A., Dasgupta P. By VLSI Design - (2015)
Adaptive Sharing of Sampling Rates among Software Based Controllers Raha R., Dey S. , Dasgupta P. By Multiconference on Systems and Control (MSC) - (2015)
Acceptance and Random Generation of Event Sequences under Real Time Calculus constraints Banerjee K., Dasgupta P. By of Design Automation and Test in Europe (DATE) 2014 - (2014)
Acceptance and Random Generation of Event Sequences under Real Time Calculus constraints Banerjee K., Dasgupta P. By of Design Automation and Test in Europe (DATE) 2014 - (2014)
Synthesis of Sampling Modes for Adaptive Control Raha R., Hazra A. , Mondal A. , Dey S. , Chakrabarti P. P., Dasgupta P. By International Conference on Control System, Computing and Engineering - (2014)
Synthesis of Sampling Modes for Adaptive Control Raha R., Hazra A. , Mondal A. , Dey S. , Chakrabarti P. P., Dasgupta P. By International Conference on Control System, Computing and Engineering - (2014)
Formal Verification of Hardware/Software Power Management Strategies Mukherjee R., Dasgupta P. , Pal A. , Mukherjee S. By VLSI Design - (2013)
Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures Ghosh P., Sharma A. , Chakrabarti P. P., Dasgupta P. By 23rd International Joint Conference on Artificial Intelligence (IJCAI) 3156-3160 (2013)
Formal Verification of Hardware/Software Power Management Strategies Mukherjee R., Dasgupta P. , Pal A. , Mukherjee S. By VLSI Design - (2013)
Handling Fault Detection Latencies in Automata-based Scheduling for Embedded Control Software M S. P., Hazra A. , Dasgupta P. , Chakrabarti P. P. By Multi-Conference on Systems and Control (MSC) - (2013)
Handling Fault Detection Latencies in Automata-based Scheduling for Embedded Control Software M S. P., Hazra A. , Dasgupta P. , Chakrabarti P. P. By Multi-Conference on Systems and Control (MSC) - (2013)
Model Checking Controllers with Predicate Inputs M S. P., Dasgupta P. By VLSI Design - (2013)
Model Checking of Global Power Management Strategies in Software with Temporal Logic Properties Mukherjee R., Mukherjee S. , Dasgupta P. By 6th India Software Engineering Conference (ISEC) - (2013)
Ordered Solution Generation for Implicit AND/OR Search Spaces Ghosh P., Chakrabarti P. P., Dasgupta P. By PReMI - (2013)
Model Checking Controllers with Predicate Inputs M S. P., Dasgupta P. By VLSI Design - (2013)
Model Checking of Global Power Management Strategies in Software with Temporal Logic Properties Mukherjee R., Mukherjee S. , Dasgupta P. By 6th India Software Engineering Conference (ISEC) - (2013)
Debugging Assertion Failures in Software Controllers using a Reference Model Banerjee K., M S. P., Dasgupta P. By 6th India Software Engineering Conference (ISEC) - (2013)
Ordered Solution Generation for Implicit AND/OR Search Spaces Ghosh P., Chakrabarti P. P., Dasgupta P. By PReMI - (2013)
Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures Ghosh P., Sharma A. , Chakrabarti P. P., Dasgupta P. By 23rd International Joint Conference on Artificial Intelligence (IJCAI) 3156-3160 (2013)
Debugging Assertion Failures in Software Controllers using a Reference Model Banerjee K., M S. P., Dasgupta P. By 6th India Software Engineering Conference (ISEC) - (2013)
Reliability Annotations to Formal Specifications of Context-Sensitive Safety Properties in Embedded Systems Hazra A., Ghosh P. , Dasgupta P. By Forum on Specification and Design Languages (FDL) - (2012)
Execution Ordering in AND/OR Graphs with Failure Probabilities Ghosh P., Chakrabarti P. P., Dasgupta P. By 5th Annual Symposium on Combinatorial Search (SOCS) - (2012)
Execution Ordering in AND/OR Graphs with Failure Probabilities Ghosh P., Chakrabarti P. P., Dasgupta P. By 5th Annual Symposium on Combinatorial Search (SOCS) - (2012)
Formal Methods for Coverage Analysis of Architectural Power States in Power-Managed Designs Hazra A., Dasgupta P. , Banerjee A. , Harer K. By 17th Asia and South Pacific Design Automation Conference (ASP-DAC) 585-590 (2012)
Formal Methods for Coverage Analysis of Architectural Power States in Power-Managed Designs Hazra A., Dasgupta P. , Banerjee A. , Harer K. By 17th Asia and South Pacific Design Automation Conference (ASP-DAC) 585-590 (2012)
Formal Methods for Ranking Counterexamples Through Assumption Mining Mitra S., Banerjee A. , Dasgupta P. By Design Automation and Test in Europe (DATE) 2012 - (2012)
Formal Methods for Ranking Counterexamples Through Assumption Mining Mitra S., Banerjee A. , Dasgupta P. By Design Automation and Test in Europe (DATE) 2012 - (2012)
A Generalized Theory for Formal Assertion Coverage Das S., Banerjee A. , Dasgupta P. By Asian Test Symposium (ATS) - (2012)
A Library for Passive Online Verification of Analog and Mixed-Signal Circuits Pal D., Dasgupta P. , Mukhopadhyay S. By VLSI Design 364-369 (2012)
Multi-Objective Low-power CDFG Scheduling using Fine-Grained DVS Architecture in Distributed Framework Mukherjee R., Ghosh P. , Kumar N. S., Dasgupta P. , Pal A. By International Symposium on Electronic System Design (ISED) - (2012)
Workload Driven Power Domain Partitioning Dobriyal A., Gonnabattula R. , Dasgupta P. , Mandal C. By VLSI Design and Test (VDAT) 147-155 (2012)
Anytime Algorithms for Biobjective Heuristic Search Ghosh P., Chakrabarti P. P., Dasgupta P. By 25th Australasian Joint Conference on Artificial Intelligence - (2012)
Operator Scheduling Revisited : A Multi-Objective Perspective for Fine-Grained DVS Architecture Mukherjee R., Ghosh P. , Dasgupta P. , Pal A. By 2nd International Conference on Advances in Computing and Information Technology (ACITY) 633-648 (2012)
Planning with Action Prioritization and new Benchmarks for Classical Planning Ghosh K., Dasgupta P. , Ramesh S. By 25th Australasian Joint Conference on Artificial Intelligence - (2012)
Reliability Annotations to Formal Specifications of Context-Sensitive Safety Properties in Embedded Systems Hazra A., Ghosh P. , Dasgupta P. By Forum on Specification and Design Languages (FDL) - (2012)
Multi-Objective Low-power CDFG Scheduling using Fine-Grained DVS Architecture in Distributed Framework Mukherjee R., Ghosh P. , Kumar N. S., Dasgupta P. , Pal A. By International Symposium on Electronic System Design (ISED) - (2012)
A Generalized Theory for Formal Assertion Coverage Das S., Banerjee A. , Dasgupta P. By Asian Test Symposium (ATS) - (2012)
A Library for Passive Online Verification of Analog and Mixed-Signal Circuits Pal D., Dasgupta P. , Mukhopadhyay S. By VLSI Design 364-369 (2012)
Operator Scheduling Revisited : A Multi-Objective Perspective for Fine-Grained DVS Architecture Mukherjee R., Ghosh P. , Dasgupta P. , Pal A. By 2nd International Conference on Advances in Computing and Information Technology (ACITY) 633-648 (2012)
Planning with Action Prioritization and new Benchmarks for Classical Planning Ghosh K., Dasgupta P. , Ramesh S. By 25th Australasian Joint Conference on Artificial Intelligence - (2012)
Anytime Algorithms for Biobjective Heuristic Search Ghosh P., Chakrabarti P. P., Dasgupta P. By 25th Australasian Joint Conference on Artificial Intelligence - (2012)
Workload Driven Power Domain Partitioning Dobriyal A., Gonnabattula R. , Dasgupta P. , Mandal C. By VLSI Design and Test (VDAT) 147-155 (2012)
Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions Mukherjee S., Dasgupta P. By VLSI Design - (2011)
Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces Komuravelli A., Mitra S. , Banerjee A. , Dasgupta P. By Asian Test Symposium (ATS) 238-243 (2011)
POWER-SIM : An SOC Simulator for Estimating Power Profiles of Mobile Workloads Ghosh P., Hazra A. , Bhilegaonkar N. , Dasgupta P. , Mandal C. , Paul K. By International Symposium on Electronic System Design (ISED) 273-278 (2011)
POWER-SIM : An SOC Simulator for Estimating Power Profiles of Mobile Workloads Ghosh P., Hazra A. , Bhilegaonkar N. , Dasgupta P. , Mandal C. , Paul K. By International Symposium on Electronic System Design (ISED) 273-278 (2011)
Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions Mukherjee S., Dasgupta P. By VLSI Design - (2011)
Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces Komuravelli A., Mitra S. , Banerjee A. , Dasgupta P. By Asian Test Symposium (ATS) 238-243 (2011)
Coverage Management with Inline Assertions and Formal Test Points Hazra A., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By VLSI Design - (2010)
Leveraging UPF-Extracted Assertions for Modeling and Formal Verification of Architectural Power Intent Hazra A., Mitra S. , Dasgupta P. , Pal A. , Bagchi D. , Guha K. By Design Automation Conference (DAC) - (2010)
Leveraging UPF-Extracted Assertions for Modeling and Formal Verification of Architectural Power Intent Hazra A., Mitra S. , Dasgupta P. , Pal A. , Bagchi D. , Guha K. By Design Automation Conference (DAC) - (2010)
Accelerating Synchronous Sequential Circuits using an Adaptive Clock Mandal A., Chakrabarti P. P., Dasgupta P. By VLSI Design - (2010)
Taming the Component Timing: A CBD Methodology for Real-time Embedded Systems Dixit M., Ramesh S. , Dasgupta P. By DATE 2010 - (2010)
A Formal Method for Detecting Semantic Conflicts in Protocols between Services with Different Ontologies Ghosh P., Dasgupta P. By Web & Semantic Technology (WeST) - (2010)
A Query based formal security analysis framework for enterprise LAN Bera P., Maity S. , Ghosh S. K., Dasgupta P. By 10th International Conference on Computer and Information Technology 2010 (CIT 2010) - (2010)
A Spatio-temporal Role-based Access Control Model for Wireless LAN Security Policy Management Bera P., Dasgupta P. , Ghosh S. K. By 4th International Conference on Information Systems, Technology and Management (ICISTM-10) - (2010)
A Study of Modeling Techniques in use in Digital and Mixed-Signal Domains for Semi-Formal Verification Mitra S., Ain A. , Ghosh P. , Dasgupta P. By TechSym - (2010)
Taming the Component Timing: A CBD Methodology for Real-time Embedded Systems Dixit M., Ramesh S. , Dasgupta P. By DATE 2010 - (2010)
Auto-Generation of AMS Behavioral Models in Different Languages from Hybrid Automata Ain A., Dasgupta P. By TechSym - (2010)
Coverage Management with Inline Assertions and Formal Test Points Hazra A., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By VLSI Design - (2010)
Accelerating Synchronous Sequential Circuits using an Adaptive Clock Mandal A., Chakrabarti P. P., Dasgupta P. By VLSI Design - (2010)
A Formal Method for Detecting Semantic Conflicts in Protocols between Services with Different Ontologies Ghosh P., Dasgupta P. By Web & Semantic Technology (WeST) - (2010)
A Query based formal security analysis framework for enterprise LAN Bera P., Maity S. , Ghosh S. K., Dasgupta P. By 10th International Conference on Computer and Information Technology 2010 (CIT 2010) - (2010)
A Spatio-temporal Role-based Access Control Model for Wireless LAN Security Policy Management Bera P., Dasgupta P. , Ghosh S. K. By 4th International Conference on Information Systems, Technology and Management (ICISTM-10) - (2010)
A Study of Modeling Techniques in use in Digital and Mixed-Signal Domains for Semi-Formal Verification Mitra S., Ain A. , Ghosh P. , Dasgupta P. By TechSym - (2010)
Auto-Generation of AMS Behavioral Models in Different Languages from Hybrid Automata Ain A., Dasgupta P. By TechSym - (2010)
Inline Assertions - Embedding Formal Properties in a Test Bench Hazra A., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By VLSI Design - (2009)
A Novel Methodology to Assist Client Side Testing of Interactive Web Applications Ghosh P., Mitra S. , Dasgupta P. By International Conference on Information Technology (ICIT) - (2009)
Assertion-Based Verification of Mixed-Signal Behaviors with Sampling Clock Mukherjee S., Panda S. K., Dasgupta P. By SNUG - (2009)
A Verification Framework for Analyzing Security Implementations in an Enterprise LAN Bera P., Dasgupta P. , Ghosh S. K. By International Advance Computing Conference (IACC) 1008-1015 (2009)
Directed Automated Symbolic Verification Of Formal Properties With Local Variables Das S., Dasgupta P. , Banerjee A. , Das P. P. By TENCON - (2009)
Fault Analysis of Security Policy Implementations in Enterprise Networks Bera P., Dasgupta P. , Ghosh S. K. By International Conference on Networks & Communications (NetCoM) - (2009)
Abstraction Refinement for State Space Partitioning based on Auxiliary State Machines Ghosh P., Ramesh B. , Banerjee A. , Dasgupta P. By TENCON - (2009)
Formal Verification of Security Policy Implementations in Enterprise Networks Bera P., Dasgupta P. , Ghosh S. K. By 5th International Conference of Information System Security (ICISS) - (2009)
A Formal Approach for Specification-Driven AMS Behavioral Model Generation Mukherjee S., Ain A. , Panda S. K., Mukhopadhyay R. , Dasgupta P. By DATE 2009 - (2009)
A Novel Methodology to Assist Client Side Testing of Interactive Web Applications Ghosh P., Mitra S. , Dasgupta P. By International Conference on Information Technology (ICIT) - (2009)
Assertion-Based Verification of Mixed-Signal Behaviors with Sampling Clock Mukherjee S., Panda S. K., Dasgupta P. By SNUG - (2009)
A Verification Framework for Analyzing Security Implementations in an Enterprise LAN Bera P., Dasgupta P. , Ghosh S. K. By International Advance Computing Conference (IACC) 1008-1015 (2009)
Incorporating Local Variables in Mixed-Signal Assertions Mukherjee S., Dasgupta P. By TENCON - (2009)
Incremental Verification Techniques for an Updated Architectural Specification Mitra S., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By INDICON - (2009)
Inline Assertions - Embedding Formal Properties in a Test Bench Hazra A., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By VLSI Design - (2009)
Directed Automated Symbolic Verification Of Formal Properties With Local Variables Das S., Dasgupta P. , Banerjee A. , Das P. P. By TENCON - (2009)
Abstraction Refinement for State Space Partitioning based on Auxiliary State Machines Ghosh P., Ramesh B. , Banerjee A. , Dasgupta P. By TENCON - (2009)
A Formal Approach for Specification-Driven AMS Behavioral Model Generation Mukherjee S., Ain A. , Panda S. K., Mukhopadhyay R. , Dasgupta P. By DATE 2009 - (2009)
Fault Analysis of Security Policy Implementations in Enterprise Networks Bera P., Dasgupta P. , Ghosh S. K. By International Conference on Networks & Communications (NetCoM) - (2009)
Formal Verification of Security Policy Implementations in Enterprise Networks Bera P., Dasgupta P. , Ghosh S. K. By 5th International Conference of Information System Security (ICISS) - (2009)
Incorporating Local Variables in Mixed-Signal Assertions Mukherjee S., Dasgupta P. By TENCON - (2009)
Incremental Verification Techniques for an Updated Architectural Specification Mitra S., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By INDICON - (2009)
CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications Banerjee A., Datta K. , Dasgupta P. By Advanced Technology for Verification and Analysis (ATVA) 228-233 (2008)
Cohesive Coverage Management for Simulation and Formal Property Verification Hazra A., Banerjee A. , Mitra S. , Dasgupta P. , Chakrabarti P. P., Mohan C. R. By IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 251-256 (2008)
Quantified UML Collaboration Diagrams Worah P., Banerjee A. , Chakrabarti P. P., Dasgupta P. By VLSI Design and Test Symposium - (2008)
Dynamic Assertion-based Verification Platform for UML Statecharts over Rhapsody Banerjee A., Ray S. , Dasgupta P. , Chakrabarti P. P., Ramesh S. , Ganesan P. By Advanced Technology for Verification and Analysis (ATVA) 222-227 (2008)
CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications Banerjee A., Datta K. , Dasgupta P. By Advanced Technology for Verification and Analysis (ATVA) 228-233 (2008)
Cohesive Coverage Management for Simulation and Formal Property Verification Hazra A., Banerjee A. , Mitra S. , Dasgupta P. , Chakrabarti P. P., Mohan C. R. By IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 251-256 (2008)
Quantified UML Collaboration Diagrams Worah P., Banerjee A. , Chakrabarti P. P., Dasgupta P. By VLSI Design and Test Symposium - (2008)
Dynamic Assertion-based Verification Platform for UML Statecharts over Rhapsody Banerjee A., Ray S. , Dasgupta P. , Chakrabarti P. P., Ramesh S. , Ganesan P. By Advanced Technology for Verification and Analysis (ATVA) 222-227 (2008)
Timing analysis of sequential circuits using symbolic event propagation Mandal A., Dasgupta P. , Chakrabarti P. P. By International Conference on Computing: Theory and Applications, Platinum Jubilee conference of ISI Kolkata - (2007)
Bounded Delay Timing Analysis using Boolean Satisfiability Roy S., Chakrabarti P. P., Dasgupta P. By VLSI Design - (2007)
A New Pseudo-Boolean Satisfiability based Approach to Power Mode Schedulabity Analysis Ray S., Dasgupta P. , Chakrabarti P. P. By VLSI Design - (2007)
Debugging Assume-Guarantee Specifications for Compositional Verification Nandi A., Pal B. , Dasgupta P. By VDAT - (2007)
Bounded Delay Timing Analysis using Boolean Satisfiability Roy S., Chakrabarti P. P., Dasgupta P. By VLSI Design - (2007)
Debugging Assume-Guarantee Specifications for Compositional Verification Nandi A., Pal B. , Dasgupta P. By VDAT - (2007)
On the realizability of specifications having auxiliary state machines and GR(1) LTL Banerjee A., Dasgupta P. , Chakrabarti P. P. By VDAT - (2007)
Timing analysis of sequential circuits using symbolic event propagation Mandal A., Dasgupta P. , Chakrabarti P. P. By International Conference on Computing: Theory and Applications, Platinum Jubilee conference of ISI Kolkata - (2007)
On the realizability of specifications having auxiliary state machines and GR(1) LTL Banerjee A., Dasgupta P. , Chakrabarti P. P. By VDAT - (2007)
A New Pseudo-Boolean Satisfiability based Approach to Power Mode Schedulabity Analysis Ray S., Dasgupta P. , Chakrabarti P. P. By VLSI Design - (2007)
Instruction set extension exploration using Decomposable Heuristic Search Das S., Chakrabarti P. P., Dasgupta P. By VLSI Design - (2006)
A Debugging Utility for Assertion-based Protocol Verification Pal B., Nandi A. , Dasgupta P. , Chakrabarti P. P. By EAIT - (2006)
Synthesis of System Verilog Assertions Das S., Mohanty R. , Dasgupta P. , Chakrabarti P. P. By DATE 06 - (2006)
Property Driven Test Generation in Absence of Direct Interface Pal B., Dasgupta P. , Chakrabarti P. P. By INDICON 15-17 (2006)
A framework for estimating peak power in gate-level circuits Chakrabarti D., Chakrabarti P. P., Mandal A. , Dasgupta P. By In International workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - (2006)
Test Generation Games from Formal Specifications Banerjee A., Pal B. , Das S. , Kumar A. , Dasgupta P. By Design Automation Conference (DAC) - (2006)
Synthesis of System Verilog Assertions Das S., Mohanty R. , Dasgupta P. , Chakrabarti P. P. By DATE 06 - (2006)
Test Generation Games from Formal Specifications Banerjee A., Pal B. , Das S. , Kumar A. , Dasgupta P. By Design Automation Conference (DAC) - (2006)
What lies between Design Intent Coverage and Model checking? Das S., Basu P. , Dasgupta P. , Chakrabarti P. P. By DATE 06 - (2006)
What lies between Design Intent Coverage and Model checking? Das S., Basu P. , Dasgupta P. , Chakrabarti P. P. By DATE 06 - (2006)
Automatic Test Generation for Temporal Coverage Points using a Stochastic Tree Model Nandi A., Pal B. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2006)
Detecting faults at the time they occur Kumar A., Das S. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2006)
Discovering input assumptions in specification refinement coverage Basu P., Das S. , Dasgupta P. , Chakrabarti P. P. By ASPDAC 06 - (2006)
Exact method for estimating Expected Settling Power in Sequential Circuits Chakraborty D., Chakrabarti P. P., Dasgupta P. By VDAT - (2006)
Formal Verification of Power Scheduling Policies for Battery Powered Mobile Systems Ray S., Dasgupta P. , Chakrabarti P. P. By INDICON 15-17 (2006)
A Debugging Utility for Assertion-based Protocol Verification Pal B., Nandi A. , Dasgupta P. , Chakrabarti P. P. By EAIT - (2006)
A framework for estimating peak power in gate-level circuits Chakrabarti D., Chakrabarti P. P., Mandal A. , Dasgupta P. By In International workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - (2006)
Instruction set extension exploration using Decomposable Heuristic Search Das S., Chakrabarti P. P., Dasgupta P. By VLSI Design - (2006)
Automatic Test Generation for Temporal Coverage Points using a Stochastic Tree Model Nandi A., Pal B. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2006)
Detecting faults at the time they occur Kumar A., Das S. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2006)
Discovering input assumptions in specification refinement coverage Basu P., Das S. , Dasgupta P. , Chakrabarti P. P. By ASPDAC 06 - (2006)
Exact method for estimating Expected Settling Power in Sequential Circuits Chakraborty D., Chakrabarti P. P., Dasgupta P. By VDAT - (2006)
Formal Verification of Power Scheduling Policies for Battery Powered Mobile Systems Ray S., Dasgupta P. , Chakrabarti P. P. By INDICON 15-17 (2006)
Property Driven Test Generation in Absence of Direct Interface Pal B., Dasgupta P. , Chakrabarti P. P. By INDICON 15-17 (2006)
SAT based solutions for Consistency Problems in Formal Property Specifications for Open Systems Roy S., Basu P. , Das S. , Dasgupta P. , Chakrabarti P. P. By ICCAD 05 885-888 (2005)
Scoreboard Directed Dynamic Constraint Modification for Higher Simulation Coverage Pal B., Nandi A. , Ray S. , Banerjee A. , Dasgupta P. , Chakrabarti P. P. By SNUG - (2005)
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-modules to Modules Basu P., Dasgupta P. , Chakrabarti P. P. By VLSI 05 - (2005)
Syntax-driven Approximate Coverage Analysis for an Assertion Suite against a High-Level Fault Model Das S., Basu P. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2005)
Test Plan Coverage by Formal Property Verification Basu P., Das S. , Banerjee A. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2005)
Bounded Model Checking for OpenLTL Roy S., Dasgupta P. , Chakrabarti P. P. By VDAT - (2005)
Bounded Model Checking for OpenLTL Roy S., Dasgupta P. , Chakrabarti P. P. By VDAT - (2005)
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model Das S., Banerjee A. , Basu P. , Dasgupta P. , Chakrabarti P. P., Mohan C. By VLSI 05 - (2005)
H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions Nandi A., Pal B. , Chhetan N. , Dasgupta P. , Chakrabarti P. P. By INDICON - (2005)
Interactive Test-Bench Synthesis for Assertion-Based Verification. In Proceedings Banerjee A., Chakravorty S. , Pal B. , Dasgupta P. By INDICON - (2005)
SAT based solutions for Consistency Problems in Formal Property Specifications for Open Systems Roy S., Basu P. , Das S. , Dasgupta P. , Chakrabarti P. P. By ICCAD 05 885-888 (2005)
Scoreboard Directed Dynamic Constraint Modification for Higher Simulation Coverage Pal B., Nandi A. , Ray S. , Banerjee A. , Dasgupta P. , Chakrabarti P. P. By SNUG - (2005)
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-modules to Modules Basu P., Dasgupta P. , Chakrabarti P. P. By VLSI 05 - (2005)
Syntax-driven Approximate Coverage Analysis for an Assertion Suite against a High-Level Fault Model Das S., Basu P. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2005)
Test Plan Coverage by Formal Property Verification Basu P., Das S. , Banerjee A. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2005)
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model Das S., Banerjee A. , Basu P. , Dasgupta P. , Chakrabarti P. P., Mohan C. By VLSI 05 - (2005)
H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions Nandi A., Pal B. , Chhetan N. , Dasgupta P. , Chakrabarti P. P. By INDICON - (2005)
Interactive Test-Bench Synthesis for Assertion-Based Verification. In Proceedings Banerjee A., Chakravorty S. , Pal B. , Dasgupta P. By INDICON - (2005)
Formal Verification Coverage: Are the RTL Properties Covering the Design's Architectural Intent? Basu P., Das S. , Dasgupta P. , Chakrabarti P. P., Mandal C. , Fix L. By DATE 2004 - (2004)
Formal Verification Coverage: Computing the Coverage Gap between Temporal Specifications Das S., Basu P. , Banerjee A. , Dasgupta P. , Chakrabarti P. P., Mohan C. , Fix L. , Armoni R. By ICCAD 04 - (2004)
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification Basu P., Dasgupta P. , Chakrabarti P. P., Mohan C. R. By VLSI, 2004 - (2004)
Formal Verification of Modules under Real Time Environment Constraints Banerjee A., Dasgupta P. , Chakrabarti P. P. By VLSI, 2004 - (2004)
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification Basu P., Dasgupta P. , Chakrabarti P. P., Mohan C. R. By VLSI, 2004 - (2004)
The BUSpec Platform for Automated Generation of Verification Aids for Standard Bus Protocols Pal B., Banerjee A. , Dasgupta P. , Chakrabarti P. P. By MEMOCODE 2004 - (2004)
The BUSpec Platform for Automated Generation of Verification Aids for Standard Bus Protocols Pal B., Banerjee A. , Dasgupta P. , Chakrabarti P. P. By MEMOCODE 2004 - (2004)
An Assertion-based Language for Generating Test Sequences for Complex Temporal Behavior Roy P., Dasgupta P. , Chakrabarti P. P. By VDAT - (2004)
A Simulation Coverage Metric for Analyzing the Behavioral Coverage of an Assertion Based Verification IP Pal B., Banerjee A. , Chaitanya K. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2004)
Assertion-based Verification: Have I written Enough Properties? Banerjee A., Pal B. , Chaitanya K. , Dasgupta P. , Chakrabarti P. P., Jha M. By INDICON 04 - (2004)
Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures Chatterjee K., Dasgupta P. , Chakrabarti P. P. By IWDC, 2004 102-113 (2004)
Design Issues for Assertion-Based Verification IPs: The OVA Experience Banerjee A., Pal B. , Dasgupta P. , Chakrabarti P. P., Jha M. , Cerny E. By SNUG - (2004)
Formal Verification Coverage: Are the RTL Properties Covering the Design's Architectural Intent? Basu P., Das S. , Dasgupta P. , Chakrabarti P. P., Mandal C. , Fix L. By DATE 2004 - (2004)
Formal Verification Coverage: Computing the Coverage Gap between Temporal Specifications Das S., Basu P. , Banerjee A. , Dasgupta P. , Chakrabarti P. P., Mohan C. , Fix L. , Armoni R. By ICCAD 04 - (2004)
Formal Verification of Modules under Real Time Environment Constraints Banerjee A., Dasgupta P. , Chakrabarti P. P. By VLSI, 2004 - (2004)
An Assertion-based Language for Generating Test Sequences for Complex Temporal Behavior Roy P., Dasgupta P. , Chakrabarti P. P. By VDAT - (2004)
A Simulation Coverage Metric for Analyzing the Behavioral Coverage of an Assertion Based Verification IP Pal B., Banerjee A. , Chaitanya K. , Dasgupta P. , Chakrabarti P. P. By VDAT - (2004)
Assertion-based Verification: Have I written Enough Properties? Banerjee A., Pal B. , Chaitanya K. , Dasgupta P. , Chakrabarti P. P., Jha M. By INDICON 04 - (2004)
Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures Chatterjee K., Dasgupta P. , Chakrabarti P. P. By IWDC, 2004 102-113 (2004)
Design Issues for Assertion-Based Verification IPs: The OVA Experience Banerjee A., Pal B. , Dasgupta P. , Chakrabarti P. P., Jha M. , Cerny E. By SNUG - (2004)
Open Computation Tree Logic With Fairness Banerjee A., Dasgupta P. , Chakrabarti P. P. By International Symposium on Circuits and Systems (ISCAS) - (2003)
Open Computation Tree Logic With Fairness Banerjee A., Dasgupta P. , Chakrabarti P. P. By International Symposium on Circuits and Systems (ISCAS) - (2003)
Open Computation Tree Logic for Formal Verification of Modules Dasgupta P., Chakrabarti A. , Chakrabarti P. P. By Asia Pacific Design Automation Conference - (2002)
Formal Verification of Module Interfaces against Real Time Specifications Chakrabarti A., Dasgupta P. , Chakrabarti P. P., Banerjee A. By Design Automation Conference (DAC) - (2002)
Open Computation Tree Logic for Formal Verification of Modules Dasgupta P., Chakrabarti A. , Chakrabarti P. P. By Asia Pacific Design Automation Conference - (2002)
Formal Verification of Module Interfaces against Real Time Specifications Chakrabarti A., Dasgupta P. , Chakrabarti P. P., Banerjee A. By Design Automation Conference (DAC) - (2002)
Symbolic verification of boolean constraints over partially specified functions Sriram S., Tandon R. , Dasgupta P. , Chakrabarti P. P. By . IEEE International Symposium on Circuits and Systems (ISCAS 2001) - (2001)
Verification of Concurrent Communicating Systems in Boolean SDL Pathak A., Bhattacharya I. , Dasgupta A. , Chakrabarti P. P., Dasgupta P. By Intell. Comput and VLSI - (2001)
Weighted Quantified Computation Tree Logic Chatterjee K., Dasgupta P. , Chakrabarti P. P. By Conf. On Information Technology (CIT'01) - (2001)
Abstraction of word-level linear arithmetic functions from bit-level component descriptions Dasgupta P., Chakrabarti P. P., Nandi A. , Krishna S. , Chakrabarti A. By Design Automation and Test in Europe (DATE) - (2001)
Abstractions for Model Checking of Event Timings Deka J. K., Chaki S. , Dasgupta P. , Chakrabarti P. P. By IEEE International Symposium on Circuits and Systems (ISCAS 2001) - (2001)
Symbolic verification of boolean constraints over partially specified functions Sriram S., Tandon R. , Dasgupta P. , Chakrabarti P. P. By . IEEE International Symposium on Circuits and Systems (ISCAS 2001) - (2001)
Abstraction of word-level linear arithmetic functions from bit-level component descriptions Dasgupta P., Chakrabarti P. P., Nandi A. , Krishna S. , Chakrabarti A. By Design Automation and Test in Europe (DATE) - (2001)
Abstractions for Model Checking of Event Timings Deka J. K., Chaki S. , Dasgupta P. , Chakrabarti P. P. By IEEE International Symposium on Circuits and Systems (ISCAS 2001) - (2001)
Verification of Concurrent Communicating Systems in Boolean SDL Pathak A., Bhattacharya I. , Dasgupta A. , Chakrabarti P. P., Dasgupta P. By Intell. Comput and VLSI - (2001)
Weighted Quantified Computation Tree Logic Chatterjee K., Dasgupta P. , Chakrabarti P. P. By Conf. On Information Technology (CIT'01) - (2001)
A comparative analysis of BDD-based and rule-based reachability problems for Cellular Automata Deka J. K., Dasgupta P. , Chakrabarti P. P. By ICCCD 2000 - (2000)
Specification of Planning Goals in Branching Time Logics in Stochastic Systems Sarkar S., Chakrabarti P. P., Niyogi R. , Dasgupta P. By Knowledge Based Computer Systems (KBCS-2000) 422-433 (2000)
Specification of Planning Goals in Branching Time Logics in Stochastic Systems Sarkar S., Chakrabarti P. P., Niyogi R. , Dasgupta P. By Knowledge Based Computer Systems (KBCS-2000) 422-433 (2000)
A comparative analysis of BDD-based and rule-based reachability problems for Cellular Automata Deka J. K., Dasgupta P. , Chakrabarti P. P. By ICCCD 2000 - (2000)
Adaptive algorithms for scheduling static task graphs in dynamic distributed systems Das P., Das D. , Dasgupta P. By HiPC'99 143-150 (1999)
Adaptive algorithms for scheduling static task graphs in dynamic distributed systems Das P., Das D. , Dasgupta P. By HiPC'99 143-150 (1999)
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays Deka J., Dasgupta P. , Chakrabarti P. P. By IEEE VLSI Design'99 294-299 (1999)
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays Deka J., Dasgupta P. , Chakrabarti P. P. By IEEE VLSI Design'99 294-299 (1999)
Controlling State Explosion in Static Simulation by Selective Composition Chakrabarti P. P., Dasgupta P. , Das P. P., Roy A. , Lahiri S. , Bose M. By ACM/IEEE Int. Conf. on VLSI Design, 1999 - (1999)
Controlling State Explosion in Static Simulation by Selective Composition Chakrabarti P. P., Dasgupta P. , Das P. P., Roy A. , Lahiri S. , Bose M. By ACM/IEEE Int. Conf. on VLSI Design, 1999 - (1999)
Exploiting isomorphism for compaction and faster simulation of binary decision diagrams Chauhan P., Dasgupta P. , Chakrabarti P. P. By IEEE VLSI Design'99 - (1999)
Exploiting isomorphism for compaction and faster simulation of binary decision diagrams Chauhan P., Dasgupta P. , Chakrabarti P. P. By IEEE VLSI Design'99 - (1999)
A Heuristic Search approach to effectively solve Constraint Optimization Problems from Logical Specifications Dasgupta P., Chakrabarti P. P., Dey A. , Ghosh S. , Bibel W. By KBCS-98 39-49 (1998)
A Heuristic Search approach to effectively solve Constraint Optimization Problems from Logical Specifications Dasgupta P., Chakrabarti P. P., Dey A. , Ghosh S. , Bibel W. By KBCS-98 39-49 (1998)
A new method for transparent fault tolerance of distributed programs on a network of workstations using alternative schedules Das D., Dasgupta P. , Das P. P. By 3rd International Conf. on Algorithms and Architectures for Parallel Processing (ICA3PP) - (1997)
A new method for transparent fault tolerance of distributed programs on a network of workstations using alternative schedules Das D., Dasgupta P. , Das P. P. By 3rd International Conf. on Algorithms and Architectures for Parallel Processing (ICA3PP) - (1997)
A new competitive algorithm for Agent Searching in Unknown Streets Dasgupta P., Chakrabarti P. P., Desarkar S. By 16th FST & TCS conference 147-155 (1996)
A new competitive algorithm for Agent Searching in Unknown Streets Dasgupta P., Chakrabarti P. P., Desarkar S. By 16th FST & TCS conference 147-155 (1996)
A near optimal strategy for the extended cow-path problem in the presence of relative errors Dasgupta P., Chakrabarti P. P., Desarkar S. By 15th FST & TCS conference 22-36 (1995)
Game Tree Search under a Partial Order Dasgupta P., Chakrabarti P. P., Desarkar S. By 4th National Seminar on Theoretical Computer Science 40-52 (1995)
A near optimal strategy for the extended cow-path problem in the presence of relative errors Dasgupta P., Chakrabarti P. P., Desarkar S. By 15th FST & TCS conference 22-36 (1995)
Game Tree Search under a Partial Order Dasgupta P., Chakrabarti P. P., Desarkar S. By 4th National Seminar on Theoretical Computer Science 40-52 (1995)
Heuristic search using multiple objectives Dasgupta P., Chakrabarti P. P. By 3rd National Seminar on Theoretical Computer Science 352-364 (1994)
Multiobjective Search in VLSI Design Dasgupta P., Mitra P. , Chakrabarti P. P. By 7th IEEE Int. Conf. on VLSI Design - (1994)
Heuristic search using multiple objectives Dasgupta P., Chakrabarti P. P. By 3rd National Seminar on Theoretical Computer Science 352-364 (1994)
Multiobjective Search in VLSI Design Dasgupta P., Mitra P. , Chakrabarti P. P. By 7th IEEE Int. Conf. on VLSI Design - (1994)

Journal

Migrating Assertions from Dense to Discrete Time Mandal S., Dasgupta P. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (Accepted/In-Press)
CoVerPlan: A Comprehensive Verification Planning Framework leveraging PSS Specifications Das S., Sanyal S. , Hazra A. , Dasgupta P. By ACM Transactions on Design Automation of Electronic Systems (TODAES) 28 1-32 (2023)
The CoveRT Approach for Coverage Management in Analog and Mixed Signal Integrated Circuits Sanyal S., Dasgupta P. , Hazra A. , Das S. , Morrison S. , Surendran S. , Balasubramanian L. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 41 5695-5708 (2022)
The CoveRT Approach for Coverage Management in Analog and Mixed Signal Integrated Circuits Sanyal S., Dasgupta P., Hazra A., Das S., Morrison S., Surendran S., Balasubramanian L. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2022)
Safe and Stable RL (S2RL) Driving Policies Using Control Barrier and Control Lyapunov Functions Gangopadhyay B., Dasgupta P., Dey S. By IEEE Transactions on Intelligent Vehicles - (2022)
Usage-driven Personalization of Power Management Logic Mandal S., Hazra A. , Dasgupta P. By IEEE Embedded System Letters (ESL) 13 106-109 (2021)
SMT-based Verification of Safety-Critical Embedded Control Software Adhikary S., Gurung A. , Thakkar J. , Bruto Da Costa A. A., Dey S. , Hazra A. , Dasgupta P. By IEEE Embedded System Letters (ESL) 13 138-141 (2021)
SongF0: A Spectrum-Based Fundamental Frequency Estimation for Monophonic Songs Rengaswamy P., Rao K. S., Dasgupta P. By Circuits, Systems, and Signal Processing 40 772-797 (2021)
hf0: A Hybrid Pitch Extraction Method for Multimodal Voice Rengaswamy P., M G. R., Rao K. S., Dasgupta P. By Circuits, Systems, and Signal Processing 40 262-275 (2021)
Hierarchical Program-Triggered Reinforcement Learning Agents for Automated Driving Gangopadhyay B., Soora H., Dasgupta P. By IEEE Transactions on Intelligent Transportation Systems - (2021)
Learning Temporal Causal Sequence Relationships from Real-Time Time-Series Bruto Da Costa A. A., Dasgupta P. By Journal of Artificial Intelligence Research 70 205-243 (2021)
Semi-lexical languages: a formal basis for using domain knowledge to resolve ambiguities in deep-learning based computer vision Gangopadhyay B., Hazra S., Dasgupta P. By Pattern Recognition Letters 152 143-149 (2021)
Performance-Driven Post-Processing of Control Loop Execution Schedules Ghosh S., Dey S. , Dasgupta P. By ACM Transactions on Design Automation of Electronic Systems 26 1-27 (2021)
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation Jana R. L., Dey S. , Dasgupta P. By ACM Transactions on Design Automation of Electronic Systems 25 1-33 (2020)
Pattern Guided Integrated Scheduling and Routing in Multi-hop Control Networks Ghosh S., Dey S. , Dasgupta P. By ACM Transaction on Embedded Computing Systems 19 - (2020)
Pattern Guided Integrated Scheduling and Routing in Multi-hop Control Networks Ghosh S., Dey S. , Dasgupta P. By ACM Transaction on Embedded Computing Systems 19 - (2020)
Recurrence in Dense-time AMS Assertions Sanyal S., da Costa A.A.B., Dasgupta P. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2020)
Assertions for Protecting Mixed-Signal Latency Contracts in Power Management Mandal S., Dasgupta P. , Hazra A. , Mohan C. R. By IEEE Transactions on Very Large Scale Integrated Circuits 28 1745-1756 (2020)
Recurrence in Dense-time AMS Assertions Sanyal S., da Costa A.A.B., Dasgupta P. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2020)
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits Sanyal S., Bhattacharya M. , Patra A. , Dasgupta P. By Journal of Electronic Testing 36 719-730 (2020)
Assertions for Protecting Mixed-Signal Latency Contracts in Power Management Mandal S., Dasgupta P. , Hazra A. , Mohan C. R. By IEEE Transactions on Very Large Scale Integrated Circuits 28 1745-1756 (2020)
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation Jana R. L., Dey S. , Dasgupta P. By ACM Transactions on Design Automation of Electronic Systems 25 1-33 (2020)
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits Sanyal S., Bhattacharya M. , Patra A. , Dasgupta P. By Journal of Electronic Testing 36 719-730 (2020)
Robust f0 extraction from monophonic signals using adaptive sub-band filtering Rengaswamy P., Reddy M. K., Rao K. S., Dasgupta P. By Speech Communication 116 77-85 (2020)
Robust f0 extraction from monophonic signals using adaptive sub-band filtering Rengaswamy P., Reddy M. K., Rao K. S., Dasgupta P. By Speech Communication 116 77-85 (2020)
Automated planning for finding alternative bug traces Jana R. L., Dey S. , Mondal A. , Dasgupta P. By IET Computers & Digital Techniques 14 322-335 (2020)
Automated planning for finding alternative bug traces Jana R. L., Dey S. , Mondal A. , Dasgupta P. By IET Computers & Digital Techniques 14 322-335 (2020)
Interpreting Local Variables in AMS Assertions during Simulation Ain A., Dasgupta P. By IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 38 980-984 (2019)
An automated framework for exploitable fault identification in block ciphers Saha S., Kumar U. , Mukhopadhyay D. , Dasgupta P. By Journal of Cryptographic Engineering 9 - (2019)
An automated framework for exploitable fault identification in block ciphers Saha S., Kumar U. , Mukhopadhyay D. , Dasgupta P. By Journal of Cryptographic Engineering 9 - (2019)
Performance and Energy Aware Robust Specification of Control Execution Patterns under Dropped Samples Ghosh S., Dey S. , Dasgupta P. By IET Computers & Digital Techniques 13 493-504 (2019)
Performance and Energy Aware Robust Specification of Control Execution Patterns under Dropped Samples Ghosh S., Dey S. , Dasgupta P. By IET Computers & Digital Techniques 13 493-504 (2019)
Interpreting Local Variables in AMS Assertions during Simulation Ain A., Dasgupta P. By IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 38 980-984 (2019)
Automatic Characterization of Exploitable Faults: A Machine Learning Approach Saha S., Jap D. , Patranabis S. , Mukhopadhyay D. , Bhasin S. , Dasgupta P. By IEEE Transactions on Information Forensics and Security 14 954-968 (2018)
Formal Feature Interpretation of Hybrid Systems Costa A. A., Frehse G. , Dasgupta P. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 2474-2484 (2018)
Formal Feature Interpretation of Hybrid Systems Costa A. A., Frehse G. , Dasgupta P. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 2474-2484 (2018)
Co-synthesis of Loop Execution Patterns for Multi-Hop Control Networks Dey S., Dasgupta P. , Ghosh S. By IEEE Embedded Systems Letters 10 - (2018)
Co-synthesis of Loop Execution Patterns for Multi-Hop Control Networks Dey S., Dasgupta P. , Ghosh S. By IEEE Embedded Systems Letters 10 - (2018)
Automatic Characterization of Exploitable Faults: A Machine Learning Approach Saha S., Jap D. , Patranabis S. , Mukhopadhyay D. , Bhasin S. , Dasgupta P. By IEEE Transactions on Information Forensics and Security 14 954-968 (2018)
ExpFault: An Automated Framework for Exploitable Fault Characterization in Block Ciphers Saha S., Mukhopadhyay D. , Dasgupta P. By IACR Transactions on Cryptographic Hardware and Embedded Systems 2018 242-276 (2018)
ExpFault: An Automated Framework for Exploitable Fault Characterization in Block Ciphers Saha S., Mukhopadhyay D. , Dasgupta P. By IACR Transactions on Cryptographic Hardware and Embedded Systems 2018 242-276 (2018)
An Automated Framework for Exploitable Fault Characterization in Block Ciphers Saha S., Mukhopadhyay D. , Dasgupta P. By IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES'18) - (2018)
Interpreting Local Variables in AMS Assertions during Simulation Ain A., Dasgupta P. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2018)
Interpreting Local Variables in AMS Assertions during Simulation Ain A., Dasgupta P. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2018)
An Automated Framework for Exploitable Fault Characterization in Block Ciphers Saha S., Mukhopadhyay D. , Dasgupta P. By IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES'18) - (2018)
Algorithmic Approaches for optimizing Electronic Control Unit time using Multi-rate Sampling Raha R., Dey S. , Dasgupta P. By Journal of Control Theory and Technology 16 173-190 (2018)
Algorithmic Approaches for optimizing Electronic Control Unit time using Multi-rate Sampling Raha R., Dey S. , Dasgupta P. By Journal of Control Theory and Technology 16 173-190 (2018)
Co-synthesis of Loop Execution Patterns for Multi-Hop Control Networks Ghosh S., Dey S. , Dasgupta P. By IEEE Embedded Systems Letters - (2017)
A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control Dey S., Dasgupta P. , Ghosh S. , Dutta S. By ACM Transactions on Embedded Computing Systems (TECS) 16 - (2017)
Formal Methods for Validation and Test Point Prioritization in Railway Signaling Logic Ghosh S., Das A. , Basak N. , Dasgupta P. , Katiyar A. By IEEE Transactions on Intelligent Transportation Systems 18(3) 678-689 (2017)
Co-synthesis of Loop Execution Patterns for Multi-Hop Control Networks Ghosh S., Dey S. , Dasgupta P. By IEEE Embedded Systems Letters - (2017)
Formal Methods for Validation and Test Point Prioritization in Railway Signaling Logic Ghosh S., Das A. , Basak N. , Dasgupta P. , Katiyar A. By IEEE Transactions on Intelligent Transportation Systems 18(3) 678-689 (2017)
A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control Dey S., Dasgupta P. , Ghosh S. , Dutta S. By ACM Transactions on Embedded Computing Systems (TECS) 16 - (2017)
Multi-rate sampling for Power-Performance Tradeoff in Embedded Control Raha R., Dutta S. , Dey S. , Dasgupta P. By IEEE Embedded System Letters 8(4) 77-80 (2016)
Multi-rate sampling for Power-Performance Tradeoff in Embedded Control Raha R., Dutta S. , Dey S. , Dasgupta P. By IEEE Embedded System Letters 8(4) 77-80 (2016)
Feature Indented Assertions for Analog and Mixed-Signal Validation Ain A., Bruto Da Costa A. B., Dasgupta P. By IEEE Transactions on CAD of Integrated Circuits and Systems 35(11) 1928-1941 (2016)
Feature Indented Assertions for Analog and Mixed-Signal Validation Ain A., Bruto Da Costa A. B., Dasgupta P. By IEEE Transactions on CAD of Integrated Circuits and Systems 35(11) 1928-1941 (2016)
Formal Assessment of Reliability Specifications in Embedded Cyber-Physical Systems Hazra A., Dasgupta P. , Chakrabarti P. P. By Journal of Applied Logic (JAL) 18 71-104 (2016)
Formal Assessment of Reliability Specifications in Embedded Cyber-Physical Systems Hazra A., Dasgupta P. , Chakrabarti P. P. By Journal of Applied Logic (JAL) 18 71-104 (2016)
Formal Interpretation of Assertion Based Features on AMS Designs Bruto Da Costa A. A., Dasgupta P. By IEEE Design and Test 32(1) 9-17 (2015)
Formal Interpretation of Assertion Based Features on AMS Designs Bruto Da Costa A. A., Dasgupta P. By IEEE Design and Test 32(1) 9-17 (2015)
Online Prognosis for Priority Power Supply Restoration Ain A., Dasgupta P. By Sustainable Energy, Grids and Networks 2 61-68 (2015)
Online Prognosis for Priority Power Supply Restoration Ain A., Dasgupta P. By Sustainable Energy, Grids and Networks 2 61-68 (2015)
Automated Planning as an Early Verification Tool for Distributed Control Ghosh K., Dasgupta P. , Ramesh S. By Journal of Automated Reasoning 54 (1) 31-68 (2015)
Automated Planning as an Early Verification Tool for Distributed Control Ghosh K., Dasgupta P. , Ramesh S. By Journal of Automated Reasoning 54 (1) 31-68 (2015)
Time-Budgeting: A Component Based Development Methodology for Real-time Embedded Systems Dixit M., Ramesh S. , Dasgupta P. By Formal Aspects of Computing (FAOC) 26(3) 591-621 (2014)
Formal Hardware/Software Co-Verification of Embedded Power Controllers Dasgupta P., Srivas M. K., Mukherjee R. By IEEE Transactions on CAD of Integrated Circuits and Systems 33(12) 2025-2029 (2014)
Formal Hardware/Software Co-Verification of Embedded Power Controllers Dasgupta P., Srivas M. K., Mukherjee R. By IEEE Transactions on CAD of Integrated Circuits and Systems 33(12) 2025-2029 (2014)
Time-Budgeting: A Component Based Development Methodology for Real-time Embedded Systems Dixit M., Ramesh S. , Dasgupta P. By Formal Aspects of Computing (FAOC) 26(3) 591-621 (2014)
An Integrated Approach for Fine-Grained Power and Temperature Management During High-level Synthesis Mukherjee R., Ghosh P. , Dasgupta P. , Pal A. By Journal of Low Power Electronics (JOLPE) 9(3) 350-362 (2013)
Formal Guarantees for Localized Bug Fixes Mitra S., Banerjee A. , Dasgupta P. , Ghosh P. , Kumar H. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32 1274-1287 (2013)
Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications Hazra A., Ghosh P. , Vadlamudi S. G., Chakrabarti P. P., Dasgupta P. By Embedded Systems Letters 5(1) 8-11 (2013)
An Integrated Approach for Fine-Grained Power and Temperature Management During High-level Synthesis Mukherjee R., Ghosh P. , Dasgupta P. , Pal A. By Journal of Low Power Electronics (JOLPE) 9(3) 350-362 (2013)
Formal Verification of Architectural Power Intent Hazra A., Goyal S. , Dasgupta P. , Pal A. By IEEE Transaction on VLSI Systems (TVLSI) 21(3) 78-91 (2013)
Counterexample Ranking Using Mined Invariants Mitra S., Banerjee A. , Dasgupta P. , Kumar H. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sytems 32 1978-1991 (2013)
Post-Silicon Debugging of PMU Integration Errors using Behavioral Models Ain A., Mukherjee S. , Dasgupta P. , Mukhopadhyay S. By Integration the VLSI Journal 46(3) 310-321 (2013)
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent Hazra A., Mukherjee R. , Dasgupta P. , Pal A. , Harer K. , Banerjee A. , Mukherjee S. By IEEE Trans. on CAD of Integrated Circuits and Systems 32(11) 1801-1813 (2013)
Formal Guarantees for Localized Bug Fixes Mitra S., Banerjee A. , Dasgupta P. , Ghosh P. , Kumar H. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32 1274-1287 (2013)
Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications Hazra A., Ghosh P. , Vadlamudi S. G., Chakrabarti P. P., Dasgupta P. By Embedded Systems Letters 5(1) 8-11 (2013)
Formal Verification of Architectural Power Intent Hazra A., Goyal S. , Dasgupta P. , Pal A. By IEEE Transaction on VLSI Systems (TVLSI) 21(3) 78-91 (2013)
Counterexample Ranking Using Mined Invariants Mitra S., Banerjee A. , Dasgupta P. , Kumar H. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sytems 32 1978-1991 (2013)
Post-Silicon Debugging of PMU Integration Errors using Behavioral Models Ain A., Mukherjee S. , Dasgupta P. , Mukhopadhyay S. By Integration the VLSI Journal 46(3) 310-321 (2013)
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent Hazra A., Mukherjee R. , Dasgupta P. , Pal A. , Harer K. , Banerjee A. , Mukherjee S. By IEEE Trans. on CAD of Integrated Circuits and Systems 32(11) 1801-1813 (2013)
A Fuzzy Real Time Temporal Logic Mukherjee S., Dasgupta P. By Int. J. Approx. Reasoning 54(9) 1452-1470 (2013)
A Fuzzy Real Time Temporal Logic Mukherjee S., Dasgupta P. By Int. J. Approx. Reasoning 54(9) 1452-1470 (2013)
Reliability Guarantees in Automata Based Scheduling for Embedded Control Software M S. P., Hazra A. , Dasgupta P. By IEEE Embedded Systems Letters (ESL) 5(2) 17-20 (2013)
A Multi-Objective Perspective for Operator Scheduling using Fine-Grained DVS Architectures Mukherjee R., Ghosh P. , Dasgupta P. , Pal A. By International journal of VLSI design and Communication Systems (VLSICS) 4(1) 105-122 (2013)
Reliability Guarantees in Automata Based Scheduling for Embedded Control Software M S. P., Hazra A. , Dasgupta P. By IEEE Embedded Systems Letters (ESL) 5(2) 17-20 (2013)
A Multi-Objective Perspective for Operator Scheduling using Fine-Grained DVS Architectures Mukherjee R., Ghosh P. , Dasgupta P. , Pal A. By International journal of VLSI design and Communication Systems (VLSICS) 4(1) 105-122 (2013)
A dynamic assertion-based verification platform for validation of UML designs Banerjee A., Ray S. , Dasgupta P. , Chakrabarti P. P., Ramesh S. , Ganesan P. By ACM SIGSOFT Software Engineering Notes 37(1) 1-14 (2012)
A dynamic assertion-based verification platform for validation of UML designs Banerjee A., Ray S. , Dasgupta P. , Chakrabarti P. P., Ramesh S. , Ganesan P. By ACM SIGSOFT Software Engineering Notes 37(1) 1-14 (2012)
Early analysis of critical faults: An approach to test generation from formal specifications Das S., Banerjee A. , Dasgupta P. By IEEE Transactions on CAD (TCAD) 31 447-451 (2012)
Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures Ghosh P., Sharma A. , Chakrabarti P. P., Dasgupta P. By Journal of Artificial Intelligence Research 44 275-333 (2012)
Symbolic event propagation based minimal test set generation for robust path delay faults Mondal A., Chakrabarti P. P., Dasgupta P. By ACM Transactions on Design Automation of Electronic Systems 17(4) - (2012)
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice Mukherjee S., Dasgupta P. , Mukhopadhyay S. , Little S. , Havlicek J. , Chandrasekaran S. By ACM Trans. Design Autom. Electr. Syst 17(4) 38- (2012)
Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures Ghosh P., Sharma A. , Chakrabarti P. P., Dasgupta P. By Journal of Artificial Intelligence Research 44 275-333 (2012)
Early analysis of critical faults: An approach to test generation from formal specifications Das S., Banerjee A. , Dasgupta P. By IEEE Transactions on CAD (TCAD) 31 447-451 (2012)
Cohesive Coverage Management: Simulation Meets Formal Methods Hazra A., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By Journal of Electronic Testing: Theory and Applications (JETTA) 28 449-468 (2012)
Symbolic event propagation based minimal test set generation for robust path delay faults Mondal A., Chakrabarti P. P., Dasgupta P. By ACM Transactions on Design Automation of Electronic Systems 17(4) - (2012)
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice Mukherjee S., Dasgupta P. , Mukhopadhyay S. , Little S. , Havlicek J. , Chandrasekaran S. By ACM Trans. Design Autom. Electr. Syst 17(4) 38- (2012)
Cohesive Coverage Management: Simulation Meets Formal Methods Hazra A., Ghosh P. , Dasgupta P. , Chakrabarti P. P. By Journal of Electronic Testing: Theory and Applications (JETTA) 28 449-468 (2012)
Computing Minimal Debugging Windows in Failure Traces of AMS Assertions Mukherjee S., Dasgupta P. By IEEE Trans. on CAD of Integrated Circuits and Systems 31(11) 1776-1781 (2012)
SAT based timing analysis for fixed and rise/fall gate delay models Roy S., Chakrabarti P. P., Dasgupta P. By Integration VLSI 40(4) 357-364 (2012)
Computing Minimal Debugging Windows in Failure Traces of AMS Assertions Mukherjee S., Dasgupta P. By IEEE Trans. on CAD of Integrated Circuits and Systems 31(11) 1776-1781 (2012)
SAT based timing analysis for fixed and rise/fall gate delay models Roy S., Chakrabarti P. P., Dasgupta P. By Integration VLSI 40(4) 357-364 (2012)
Assertion Aware Sampling Refinement: A Mixed-Signal Perspective Mukherjee S., Dasgupta P. By IEEE Trans. on CAD of Integrated Circuits and Systems 31(11) 1772-1776 (2012)
Assertion Aware Sampling Refinement: A Mixed-Signal Perspective Mukherjee S., Dasgupta P. By IEEE Trans. on CAD of Integrated Circuits and Systems 31(11) 1772-1776 (2012)
Verification by parts: Reusing component invariant checking results Mitra S., Ghosh P. , Dasgupta P. By IET Computers and Digital Techniques 6 19-32 (2012)
Power-SIM: An SOC simulator for estimating power profiles of mobile workloads Ghosh P., Hazra A. , Gonnabhaktula R. , Bhilegaonkar N. , Dasgupta P. , Mandal C. , Paul K. By Journal of Low Power Electronics 8(3) 293-303 (2012)
Verification by parts: Reusing component invariant checking results Mitra S., Ghosh P. , Dasgupta P. By IET Computers and Digital Techniques 6 19-32 (2012)
Power-SIM: An SOC simulator for estimating power profiles of mobile workloads Ghosh P., Hazra A. , Gonnabhaktula R. , Bhilegaonkar N. , Dasgupta P. , Mandal C. , Paul K. By Journal of Low Power Electronics 8(3) 293-303 (2012)
Auxiliary Specifications for Context-Sensitive Monitoring of AMS assertions Mukherjee S., Dasgupta P. , Mukhopadhyay S. By IEEE Transactions on CAD (TCAD) 30(10) 1446-1457 (2011)
Auxiliary Specifications for Context-Sensitive Monitoring of AMS assertions Mukherjee S., Dasgupta P. , Mukhopadhyay S. By IEEE Transactions on CAD (TCAD) 30(10) 1446-1457 (2011)
Chassis: A Platform for Verifying PMU Integration using Auto-Generated Behavioral Models Ain A., Pal D. , Dasgupta P. , Mukhopadhyay S. , Mukhopadhyay R. , Gough J. By ACM Transactions on Design Automation of Electronic Systems 16(3) - (2011)
Chassis: A Platform for Verifying PMU Integration using Auto-Generated Behavioral Models Ain A., Pal D. , Dasgupta P. , Mukhopadhyay S. , Mukhopadhyay R. , Gough J. By ACM Transactions on Design Automation of Electronic Systems 16(3) - (2011)
Some results on Parametric Temporal Logic Dixit M., Ramesh S. , Dasgupta P. By Information Processing Letters 111(20) 994-998 (2011)
Some results on Parametric Temporal Logic Dixit M., Ramesh S. , Dasgupta P. By Information Processing Letters 111(20) 994-998 (2011)
A static verification approach for architectural integration of mixed-signal integrated circuits, Integration Mukhopadhyay R., Komuravelli A. , Dasgupta P. , Panda S. K., Mukhopadhyay S. By VLSI Journal 43(1) 58-71 (2010)
Integrated Security Analysis Framework for an Enterprise Network-A Formal Approach Bera P., Ghosh S. K., Dasgupta P. By IET Information Security 4(4) 283-300 (2010)
A WLAN security Management Framework based on Formal Spatio-Temporal RBAC Model Bera P., Ghosh S. K., Dasgupta P. By Journal of Security and Communication Networks 4 981-993 (2010)
Bounded Delay Timing Analysis and Power Estimation using SAT Roy S., Chakrabarti P. P., Dasgupta P. By Microelectronics Journal 41 (5) 317-324 (2010)
Integrated Security Analysis Framework for an Enterprise Network-A Formal Approach Bera P., Ghosh S. K., Dasgupta P. By IET Information Security 4(4) 283-300 (2010)
A static verification approach for architectural integration of mixed-signal integrated circuits, Integration Mukhopadhyay R., Komuravelli A. , Dasgupta P. , Panda S. K., Mukhopadhyay S. By VLSI Journal 43(1) 58-71 (2010)
A WLAN security Management Framework based on Formal Spatio-Temporal RBAC Model Bera P., Ghosh S. K., Dasgupta P. By Journal of Security and Communication Networks 4 981-993 (2010)
Policy Based Security Analysis in Enterprise Networks -A Formal Approach Bera P., Ghosh S. K., Dasgupta P. By IEEE Transactions on Network and Service Management 7(4) 231-243 (2010)
Policy Based Security Analysis in Enterprise Networks -A Formal Approach Bera P., Ghosh S. K., Dasgupta P. By IEEE Transactions on Network and Service Management 7(4) 231-243 (2010)
Bounded Delay Timing Analysis and Power Estimation using SAT Roy S., Chakrabarti P. P., Dasgupta P. By Microelectronics Journal 41 (5) 317-324 (2010)
Design Intent Coverage Revisited Sinha A., Dasgupta P. , Pal B. , Das S. , Basu P. , Chakrabarti P. P. By ACM Transactions on Design Automation of Electronic Systems 14 (1) 1-32 (2009)
Instrumenting AMS Assertion Verification on Commercial Platforms Mukhopadhyay R., Panda S. K., Dasgupta P. , Gough J. By ACM Transactions on Design Automation of Electronic Systems 14(2) 1-47 (2009)
Instrumenting AMS Assertion Verification on Commercial Platforms Mukhopadhyay R., Panda S. K., Dasgupta P. , Gough J. By ACM Transactions on Design Automation of Electronic Systems 14(2) 1-47 (2009)
Design Intent Coverage Revisited Sinha A., Dasgupta P. , Pal B. , Das S. , Basu P. , Chakrabarti P. P. By ACM Transactions on Design Automation of Electronic Systems 14 (1) 1-32 (2009)
Satisfiability Models for Maximum Transition Power Roy S., Chakrabarti P. P., Dasgupta P. By IEEE Transactions on VLSI Systems 16(8) 941-951 (2008)
Accelerating Assertion Coverage with Adaptive Test-benches Pal B., Banerjee A. , Sinha A. , Dasgupta P. By IEEE Transactions on CAD (TCAD) 27 967-972 (2008)
Accelerating Assertion Coverage with Adaptive Test-benches Pal B., Banerjee A. , Sinha A. , Dasgupta P. By IEEE Transactions on CAD (TCAD) 27 967-972 (2008)
Auxiliary state machines + context triggered properties in verification Banerjee A., Dasgupta P. , Chakrabarti P. P. By ACM Transactions on Design Automation of Electronic Systems 13 1-31 (2008)
Satisfiability Models for Maximum Transition Power Roy S., Chakrabarti P. P., Dasgupta P. By IEEE Transactions on VLSI Systems 16(8) 941-951 (2008)
Auxiliary state machines + context triggered properties in verification Banerjee A., Dasgupta P. , Chakrabarti P. P. By ACM Transactions on Design Automation of Electronic Systems 13 1-31 (2008)
Event propagation for accurate circuit delay calculating using SAT Roy S., Dasgupta P. , Chakrabarti P. P. By ACM Transactions on Design Automation of Electronic Systems 12(3) 1-23 (2007)
Statistical Timing Analysis using Symbolic Event Propagation Mondal A., Chakrabarti P. P., Dasgupta P. By IET Circuits, Devices & Systems 1(4) 283-291 (2007)
BUSpec: A framework for generation of verification aids for Standard Bus Protocol Specifications. Integration Pal B., Banerjee A. , Dasgupta P. , Chakrabarti P. P. By VLSI Journal 40 (13) 285-304 (2007)
Event propagation for accurate circuit delay calculating using SAT Roy S., Dasgupta P. , Chakrabarti P. P. By ACM Transactions on Design Automation of Electronic Systems 12(3) 1-23 (2007)
Statistical Timing Analysis using Symbolic Event Propagation Mondal A., Chakrabarti P. P., Dasgupta P. By IET Circuits, Devices & Systems 1(4) 283-291 (2007)
Hardware Accelerated Constrained Random Test Generation Pal B., Sinha A. , Dasgupta P. , Chakrabarti P. P., De K. By IET Computers and Digital Techniques 1(4) 423-433 (2007)
BUSpec: A framework for generation of verification aids for Standard Bus Protocol Specifications. Integration Pal B., Banerjee A. , Dasgupta P. , Chakrabarti P. P. By VLSI Journal 40 (13) 285-304 (2007)
Hardware Accelerated Constrained Random Test Generation Pal B., Sinha A. , Dasgupta P. , Chakrabarti P. P., De K. By IET Computers and Digital Techniques 1(4) 423-433 (2007)
Design Intent Coverage A New Paradigm for Formal Property Verification Basu P., Das S. , Banerjee A. , Dasgupta P. , Chakrabarti P. P., Mohan C. R., Fix L. , Armoni R. By IEEE Transactions on CAD 25(10) 1922-1934 (2006)
Design Intent Coverage A New Paradigm for Formal Property Verification Basu P., Das S. , Banerjee A. , Dasgupta P. , Chakrabarti P. P., Mohan C. R., Fix L. , Armoni R. By IEEE Transactions on CAD 25(10) 1922-1934 (2006)
The Open Family of Temporal Logics: Annotating Temporal Operators with Input Constraints Banerjee A., Dasgupta P. By ACM Transactions on Design Automation and Embedded Systems (TODAES) 10 (3) 492-522 (2005)
The Open Family of Temporal Logics: Annotating Temporal Operators with Input Constraints Banerjee A., Dasgupta P. By ACM Transactions on Design Automation and Embedded Systems (TODAES) 10 (3) 492-522 (2005)
The power of first-order quantification over states in branching and linear time temporal logics Chatterjee K., Dasgupta P. , Chakrabarti P. P. By Information Processing Letters 91 201-210 (2004)
The power of first-order quantification over states in branching and linear time temporal logics Chatterjee K., Dasgupta P. , Chakrabarti P. P. By Information Processing Letters 91 201-210 (2004)
A branching time temporal framework for Quantitative Reasoning Chatterjee K., Dasgupta P. , Chakrabarti P. P. By Journal of Automated Reasoning 30 205-232 (2003)
A branching time temporal framework for Quantitative Reasoning Chatterjee K., Dasgupta P. , Chakrabarti P. P. By Journal of Automated Reasoning 30 205-232 (2003)
Quantified Computation Tree Logic Patthak A. C., Bhattacharya I. , Dasgupta A. , Dasgupta P. , Chakrabarti P. P. By Information Processing Letters 82(3) 123-129 (2002)
Solving constraint optimization problems from CLP-style specifications using heuristic search techniques Dasgupta P., Chakrabarti P. P., Dey A. , Ghose S. , Bibel W. By IEEE Transactions in Knowledge and Data Engineering 14 (2) 353-368 (2002)
Min-max event triggered computation tree logic Dasgupta P., Chakrabarti P. P., Deka J. K. By Sadhana 27 (2) 163-180 (2002)
Quantified Computation Tree Logic Patthak A. C., Bhattacharya I. , Dasgupta A. , Dasgupta P. , Chakrabarti P. P. By Information Processing Letters 82(3) 123-129 (2002)
Min-max event triggered computation tree logic Dasgupta P., Chakrabarti P. P., Deka J. K. By Sadhana 27 (2) 163-180 (2002)
Solving constraint optimization problems from CLP-style specifications using heuristic search techniques Dasgupta P., Chakrabarti P. P., Dey A. , Ghose S. , Bibel W. By IEEE Transactions in Knowledge and Data Engineering 14 (2) 353-368 (2002)
Min-max Computation Tree Logic Dasgupta P., Deka J. K., Chakrabarti P. P. By Artificial Intelligence 127 137-162 (2001)
Min-max Computation Tree Logic Dasgupta P., Deka J. K., Chakrabarti P. P. By Artificial Intelligence 127 137-162 (2001)
Model checking on Timed Event Structures Dasgupta P., Deka J. , Chakrabarti P. P. By IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 19 601-611 (2000)
Model checking on Timed Event Structures Dasgupta P., Deka J. , Chakrabarti P. P. By IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 19 601-611 (2000)
A heuristic for the maximum processor requirement for scheduling layered task graphs with cloning Das D., Dasgupta P. , Das P. P. By Journal of Parallel and Distributed Computing 49 169-181 (1998)
A heuristic for the maximum processor requirement for scheduling layered task graphs with cloning Das D., Dasgupta P. , Das P. P. By Journal of Parallel and Distributed Computing 49 169-181 (1998)
Agreement under faulty interfaces Dasgupta P. By Information Processing Letters 65 125-129 (1997)
An Adaptive Load Balancing Algorithm Dasgupta P., Majumder A. , Bhattacharya P. , Thr V. By Journal of Parallel and Distributed Computing 42 101-108 (1997)
Agreement under faulty interfaces Dasgupta P. By Information Processing Letters 65 125-129 (1997)
An Adaptive Load Balancing Algorithm Dasgupta P., Majumder A. , Bhattacharya P. , Thr V. By Journal of Parallel and Distributed Computing 42 101-108 (1997)
Searching Game Trees under a Partial Order Dasgupta P., Chakrabarti P. P., Desarkar S. By Artificial Intelligence 82 237-257 (1996)
Agent Searching in Uniform b-ary Trees: Multiple Goals and Unequal Costs Dasgupta P., Chakrabarti P. P., Desarkar S. By . Information Processing Letters 58 311-318 (1996)
Agent Searching in Uniform b-ary Trees: Multiple Goals and Unequal Costs Dasgupta P., Chakrabarti P. P., Desarkar S. By . Information Processing Letters 58 311-318 (1996)
Multiobjective Heuristic Search of AND/OR Graphs Dasgupta P., Chakrabarti P. P., Desarkar S. By Journal of Algorithms 20 282-311 (1996)
New results on Multiobjective State Space Search Dasgupta P., Chakrabarti P. P., Desarkar S. By Sadhana 21(3) 263-290 (1996)
Searching Game Trees under a Partial Order Dasgupta P., Chakrabarti P. P., Desarkar S. By Artificial Intelligence 82 237-257 (1996)
Multiobjective Heuristic Search of AND/OR Graphs Dasgupta P., Chakrabarti P. P., Desarkar S. By Journal of Algorithms 20 282-311 (1996)
New results on Multiobjective State Space Search Dasgupta P., Chakrabarti P. P., Desarkar S. By Sadhana 21(3) 263-290 (1996)
A correction to Agent Searching in a tree and the optimality of Iterative Deepening Dasgupta P., Chakrabarti P. P., Desarkar S. By Artificial Intelligence 77 173-176 (1995)
Utility of Pathmax in Partial Order Heuristic Search Dasgupta P., Chakrabarti P. P., Desarkar S. By Information Processing Letters 55 317-322 (1995)
A correction to Agent Searching in a tree and the optimality of Iterative Deepening Dasgupta P., Chakrabarti P. P., Desarkar S. By Artificial Intelligence 77 173-176 (1995)
Utility of Pathmax in Partial Order Heuristic Search Dasgupta P., Chakrabarti P. P., Desarkar S. By Information Processing Letters 55 317-322 (1995)
Agent Searching in a tree and the optimality of Iterative Deepening Dasgupta P., Chakrabarti P. P., Desarkar S. By Artificial Intelligence 71 195-208 (1994)
Agent Searching in a tree and the optimality of Iterative Deepening Dasgupta P., Chakrabarti P. P., Desarkar S. By Artificial Intelligence 71 195-208 (1994)

Computer Science and Engineering

Faculty

Responsibilities

Research Areas

Principal Investigator

Co-Principal Investigator

Ph. D. Students

Bhushan Govind Naware

Briti Gangopadhyay

Dipayan Dewan

Kaushik Dey

Praveen Verma

Sayandeep Sanyal

Somnath Hazra

Sourav Das

Sumanta Dey

Swarnava Dey