Home > Academics > Academic Units > Departments > Computer Science and Engineering > Pallab Dasgupta
Professor
Computer Science and Engineering
Proving the correctness of safety critical systems using formal methods is one of the exciting areas in Computer Science. The Formal Verification and CAD Research Group, IIT Kharagpur is one of the leading groups in the world in this area, known for its wide range of contributions in CAD for verification of VLSI circuits, automated control systems, networks, and embedded software. The group has collaborated with many leading industries including Intel, IBM, Synopsys, Google, Motors, Indian Railways, National Semiconductors, Hindustan Aeronautics, and Semiconductor Research Corporation.
Professor Dasgupta has been named among the top 10 research contributors in Computer Science in India during the period 2002-2014 in a bibliometric study conducted by the Ministry of Science and Technology.
The words Cyber-Physical Systems and Industrial Internet of Things are buzzwords today in the EECS community. Software based embedded control is everywhere -- including home consumer electronics, power grids, handheld and wearable devices, automotive and avionics applications. CPS design requires interdisciplinary skills – control theory, electronics and design automation, and software. At IIT Kharagpur, researchers from Electrical, Electronics and Computer Science have come together to address some of the emerging research challenges in automotive control, safety critical avionic software, digital and analog integrated circuits, railway signalling and train control systems, and smart electrical grids. The formal verification and CAD research group offers an opportunity for addressing the challenges in studying such systems and proving that they are safe.
Recent focus of the research group, in addition to its traditional strengths in circuits and systems, includes automotive and avionic control systems, security of automotive electronics, railway technologies and embedded safety critical software.
Machine Learning at the Digital-Analog Boundary - A Contract Assurance Framework based on AMS Assertions Intel Corporation, Intel Labs
A Formal Coverage Management Framework for AMS Design Verification (GRC Proposal ID: P32524) Semiconductor Research Corporation
Setting up of a Digital Classroom and Laboratory for the Science of Music SRIC, IIT KHARAGPUR
Formal Modeling and Verification of Moving Block Signaling Based Train Operation Simulator for Indian Railways Science and Engineering Research Board (SERB)
Hybrid Automata Based Methods for AMS Feature Profiling Semiconductor Research Corporation
Synopsys CAD Laboratory Project Phase II Synopsys Inc.
FMSAFE: A Networked Centre for Formal Methods in Validation and Certification Procededures for Safety - Critical ICT Systems Ministry of Human Resource Development, Department of Higher Education, Government of India
FMSAFE: A Networked Centre for Formal Methods in Validation and Certification Procededures for Safety - Critical ICT Systems at IIT Kharagpur Ministry of Human Resource Development, Department of Higher Education, Government of India
Formal Methods for Verification of Power Management in Mixed Signal Designs INTEL CORPORATION, USA.
Decoding and exploring ancient classification of Indian music through machine learning method and audience response MHRD
Making of Web-Portals and allied outreach activity for Varanasi project and allied projects under SANDHI MHRD
Intel embedded innovation lablet Intel Semiconductor (US) Limited
TCG-HPL Sponsored Artificial Intelligence Research and Training at Centre of Excellence in Centre for AI at IIT Kharagpur TCG Foundation
UK India Clean Energy Research institute (UKICERI) Department of Science and Technology(DST)
Safety Assurance in Automotive Electronics Synopsys Inc.
Formal Methods for Physical Security Verification of Cryptographic Designs Against Fault Attacks Synopsys Inc.
Opened & Intelligent Plug-in Hybrid Electric Vehicle (PHEV) Technologies for Smart Indian Cities Ministry of Heavy Industries and Public Enterprises, GoI
Synthesizing test programs as directed test families for incremental CPU validation INTEL TECHNOLOGY INDIA PRIVATE LIMITED
To develop a scientific rationale of IELS (Indo-European Langauge Systems) applying a) Computational Linguistics & b) Cognitive Geo-spatial mapping approaches MHRD
Urban - design, planning & urban engineering exploration of Varanasi MHRD
SANDHI, Science -Technology & Culture - Heritage Interface by IIT Kharagpur MHRD
Modelling and validation of interlocking for railway signalling systems Research Designs & Standards Organisation (RDSO),
GENERAL MOTORS ECS CRL FOR EDUCATION General Motors Technical Centre India Pvt. Ltd.
Sumana Ghosh
Area of Research: Formal Verification
Rajorshee Raha
Area of Research: Validation of Embedded Real Time Control
Rajib Lochan Jana
Area of Research: Formal Fethods for Embedded System Design
Pradeep R
Area of Research: Music Signal Processing
Bruto Da Costa Antonio Anastasio
Area of Research: Formal Verification
Sudipa Mandal
Area of Research: Formal Verification
Thakkar Jay Ashwinbhai
Area of Research: Formal Verification
Bhushan Govind Naware
Area of Research: Formal Verification
Sayandeep Saha
Area of Research: Formal Methods in Cryptography
Sayandeep Sanyal
Area of Research: Formal Methods for Analog CAD
Praveen Verma
Area of Research: Smart Electrical Grids
