My research is focussed primarily in the area of designing various high speed parallel and pipelined VLSI architectures. Most of the works are related to the design and development of CORDIC based high throughput digital VLSI architectures for signal processing applications, ranging from those in the image processing, communication, to those in the biomedical domain. CORDIC provides an efficient and economic means of implementing transcendental functions in digital hardware that uses binary arithmetic. The developed architectures are mainly targeted to be deployed in real-time environments. One of the significant contributions is in the reduction of the latency of such pipelined structures. Though mostly the architectures designed are working in the digital domain, another significant research direction is towards the design of sampled analog architectures that can implement any digital signal processing algorithm much economically with unquantized samples using analog techniques, thereby having the best of both the analog and the digital worlds. This technique is capable of providing cost-effective solutions for the signal processing applications where a moderate accuracy of computation is sufficient. In a nutshell, my research area is mostly in the field of the design and development of high speed low latency VLSI architecture for real time signal processing applications.
Area of Research: Reduction of switching activity in VLSI systems
Area of Research: VLSI Architecture Design for High Performance Computer Arithmetic
Avishek Sinha Roy
Area of Research: VLSI Design
Rajen Kumar Patra
Area of Research: VLSI SIgnal Processing