Indian Institute of Technology Kharagpur |

Journal

A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits Karmakar R., Jana S. , Chattopadhyay S. By IEEE Transactions on Emerging Topics in Computing - (Accepted/In-Press)
A Cellular Automata Guided Two Level Obfuscation of Finite-State-Machine for IP Protection Karmakar R., Jana S. S., Chattopadhyay S. By Integration, the VLSI Journal - (Accepted/In-Press)
Efficient Key-gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption Karmakar R., Kumar H. , Chattopadhyay S. By IEEE Transactions on Emerging Topics in Computing - (Accepted/In-Press)
Task Mapping and Flow Priority Assignment of Real-Time Industrial Applications for Network-On-Chip based Design Khare A., Patil C. , Chattopadhyay S. By Microprocessors and Microsystems - (Accepted/In-Press)
Thermal-Aware Detour Routing in 3D NoCs Mukherjee P., Chatterjee N. , Chattopadhyay S. By Journal of Parallel and Distributed Computing - (Accepted/In-Press)
A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits Karmakar R., Jana S. , Chattopadhyay S. By IEEE Transactions on Emerging Topics in Computing - (Accepted/In-Press)
A Cellular Automata Guided Two Level Obfuscation of Finite-State-Machine for IP Protection Karmakar R., Jana S. S., Chattopadhyay S. By Integration, the VLSI Journal - (Accepted/In-Press)
Efficient Key-gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption Karmakar R., Kumar H. , Chattopadhyay S. By IEEE Transactions on Emerging Topics in Computing - (Accepted/In-Press)
Thermal-Aware Detour Routing in 3D NoCs Mukherjee P., Chatterjee N. , Chattopadhyay S. By Journal of Parallel and Distributed Computing - (Accepted/In-Press)
Task Mapping and Flow Priority Assignment of Real-Time Industrial Applications for Network-On-Chip based Design Khare A., Patil C. , Chattopadhyay S. By Microprocessors and Microsystems - (Accepted/In-Press)
Embedding Delay-based Physical Unclonable Function in Networks-on-Chip Prasad N., Sehwag V. , Chattopadhyay S. , Chakrabarti I. By IET Circuits, Devices and Systems 15 27-41 (2021)
Embedding Delay-based Physical Unclonable Function in Networks-on-Chip Prasad N., Sehwag V. , Chattopadhyay S. , Chakrabarti I. By IET Circuits, Devices and Systems 15 27-41 (2021)
A Scan Obfuscation Guided Design-for-Security Approach For Sequential Circuits Karmakar R., Chattopadhyay S. , Kapur R. By IEEE Transactions on Circuits and Systems II 67 546-550 (2020)
A Scan Obfuscation Guided Design-for-Security Approach For Sequential Circuits Karmakar R., Chattopadhyay S. , Kapur R. By IEEE Transactions on Circuits and Systems II 67 546-550 (2020)
Thermal-Aware Task Allocation and Scheduling fpr Periodic Real-Time Applications in Mesh based Heterogeneous NoCs Mukherjee P., Jain K. , Chattopadhyay S. By Real-Time Systems 1-36 (2019)
Thermal-aware test scheduling strategy for network-on-chip based systems Manna K., Sagar C. , Chattopadhyay S. , Sengupta I. By ACM Journal on Emerging Technologies in Computing (JETC) 15 6.1-6.27 (2019)
Thermal-Aware Task Allocation and Scheduling fpr Periodic Real-Time Applications in Mesh based Heterogeneous NoCs Mukherjee P., Jain K. , Chattopadhyay S. By Real-Time Systems 1-36 (2019)
Thermal-aware test scheduling strategy for network-on-chip based systems Manna K., Sagar C. , Chattopadhyay S. , Sengupta I. By ACM Journal on Emerging Technologies in Computing (JETC) 15 6.1-6.27 (2019)
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design Manna K., Mukherjee P. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Computers 67 528-542 (2018)
Area Constrained Performance Optimized ASNoC Synthesis with Therma-aware White Space Allocation and Redistribution Mukherjee P., D S. , Chattopadhyay S. By Integration, the VLSI Journal 60 167-189 (2018)
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design Manna K., Mukherjee P. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Computers 67 528-542 (2018)
An Energy Efficient Network-on-Chip based Reconfigurable Viterbi Decoder Architecture Prasad N., Chattopadhyay S. , Chakrabarti I. By IEEE Transactions on Circuits and Systems I 65 3543-3554 (2018)
Design and evaluation of ZMesh topology for on-chip interconnection networks Prasad N., Mukherjee P. , Chattopadhyay S. , Chakrabarti I. By Journal of Parallel and Distributed Computing 113 17-36 (2018)
Area Constrained Performance Optimized ASNoC Synthesis with Therma-aware White Space Allocation and Redistribution Mukherjee P., D S. , Chattopadhyay S. By Integration, the VLSI Journal 60 167-189 (2018)
Reliability-aware application mapping onto mesh based Network-on-Chip Chatterjee N., Mukherjee P. , Chattopadhyay S. By Integration, the VLSI Journal 62 92-113 (2018)
An Energy Efficient Network-on-Chip based Reconfigurable Viterbi Decoder Architecture Prasad N., Chattopadhyay S. , Chakrabarti I. By IEEE Transactions on Circuits and Systems I 65 3543-3554 (2018)
Task Mapping and Scheduling for Network-on-Chip based Multi-core Platform with Transient Faults Chatterjee N., Paul S. , Chattopadhyay S. By Journal of Systems Architecture 83 34-56 (2018)
Reliability-aware application mapping onto mesh based Network-on-Chip Chatterjee N., Mukherjee P. , Chattopadhyay S. By Integration, the VLSI Journal 62 92-113 (2018)
Design and evaluation of ZMesh topology for on-chip interconnection networks Prasad N., Mukherjee P. , Chattopadhyay S. , Chakrabarti I. By Journal of Parallel and Distributed Computing 113 17-36 (2018)
Task Mapping and Scheduling for Network-on-Chip based Multi-core Platform with Transient Faults Chatterjee N., Paul S. , Chattopadhyay S. By Journal of Systems Architecture 83 34-56 (2018)
Low Power Low Latency Floorplan-aware Path Synthesis in Application-Specific Network-on-Chip Design Mukherjee P., Chattopadhyay S. By Integration, the VLSI Journal 58 167-188 (2017)
Low Power Low Latency Floorplan-aware Path Synthesis in Application-Specific Network-on-Chip Design Mukherjee P., Chattopadhyay S. By Integration, the VLSI Journal 58 167-188 (2017)
Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform Chatterjee N., Paul S. , Mukherjee P. , Chattopadhyay S. By Journal of Systems Architecture 74 61-77 (2017)
Fault-tolerant dynamic task mapping and scheduling for network-on-chip-based multicore platform Chatterjee N., Paul S. , Chattopadhyay S. By ACM Transactions on Embedded Computing Systems 16 108- (2017)
Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture Soumya J., Babu K. N., Chattopadhyay S. By Journal of Circuits, Systems and Computers 26 1750-1765 (2017)
Fault-tolerant dynamic task mapping and scheduling for network-on-chip-based multicore platform Chatterjee N., Paul S. , Chattopadhyay S. By ACM Transactions on Embedded Computing Systems 16 108- (2017)
Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture Soumya J., Babu K. N., Chattopadhyay S. By Journal of Circuits, Systems and Computers 26 1750-1765 (2017)
Temperature and data size trade-off in dictionary based test data compression Karmakar R., Chattopadhyay S. By Integration, the VLSI Journal 57 20-33 (2017)
Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform Chatterjee N., Paul S. , Mukherjee P. , Chattopadhyay S. By Journal of Systems Architecture 74 61-77 (2017)
Temperature and data size trade-off in dictionary based test data compression Karmakar R., Chattopadhyay S. By Integration, the VLSI Journal 57 20-33 (2017)
In-field test for permanent faults in FIFO buffers of NoC routers B Ghoshal, K Manna, S Chattopadhyay Ghosal B., Manna K. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Very Large Scale Integration 24 393-397 (2016)
Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels D'souza S., Soumya J. , Chattopadhyay S. By ACM Transactions on Architecture and Code Optimization 12 40- (2016)
Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design Manna K., Swamy S. , Chattopadhyay S. , Sengupta I. By ACM Transactions on Embedded Computing Systems 16 24- (2016)
Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels D'souza S., Soumya J. , Chattopadhyay S. By ACM Transactions on Architecture and Code Optimization 12 40- (2016)
Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design Manna K., Swamy S. , Chattopadhyay S. , Sengupta I. By ACM Transactions on Embedded Computing Systems 16 24- (2016)
Small Test Set Generation with High Diagnosability Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R. By Journal of Circuits, Systems and Computers 25 - (2016)
Small Test Set Generation with High Diagnosability Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R. By Journal of Circuits, Systems and Computers 25 - (2016)
In-field test for permanent faults in FIFO buffers of NoC routers B Ghoshal, K Manna, S Chattopadhyay Ghosal B., Manna K. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Very Large Scale Integration 24 393-397 (2016)
A constructive heuristic for application mapping onto mesh based network-on-chip Sahu P. K., Manna K. , Shah T. , Chattopadhyay S. By Journal of Circuits, Systems and Computers 24 - (2015)
Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores Soumya J., Tiwary S. , Chattopadhyay S. By Journal of Systems Architecture 61 1-11 (2015)
Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores Soumya J., Tiwary S. , Chattopadhyay S. By Journal of Systems Architecture 61 1-11 (2015)
Scan chain masking for diagnosis of multiple chain failures in a space compaction environment Kundu S., Chattopadhyay S. , Sengupta I. , Kapur R. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 - (2015)
Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes Soumya J., Kumar K. N., Chattopadhyay S. By Journal of Systems Architecture 61 410-422 (2015)
Scan chain masking for diagnosis of multiple chain failures in a space compaction environment Kundu S., Chattopadhyay S. , Sengupta I. , Kapur R. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 - (2015)
Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes Soumya J., Kumar K. N., Chattopadhyay S. By Journal of Systems Architecture 61 410-422 (2015)
Window-based peak power model and particle swarm optimization guided 3-dimensional bin packing for soc test scheduling Karmakar R., Chattopadhyay S. By Integration, the VLSI Journal 50 61-73 (2015)
Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation Manna K., Veeramreddy C. R., Chattopadhyay S. , Sengupta I. By International Journal of High Performance Systems Architecture 5 141-152 (2015)
Window-based peak power model and particle swarm optimization guided 3-dimensional bin packing for soc test scheduling Karmakar R., Chattopadhyay S. By Integration, the VLSI Journal 50 61-73 (2015)
Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip Prasad N., Chattopadhyay S. , Chakrabarti I. By Microprocessors and Microsystems 39 741-751 (2015)
Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation Manna K., Veeramreddy C. R., Chattopadhyay S. , Sengupta I. By International Journal of High Performance Systems Architecture 5 141-152 (2015)
A constructive heuristic for application mapping onto mesh based network-on-chip Sahu P. K., Manna K. , Shah T. , Chattopadhyay S. By Journal of Circuits, Systems and Computers 24 - (2015)
Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip Prasad N., Chattopadhyay S. , Chakrabarti I. By Microprocessors and Microsystems 39 741-751 (2015)
Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip Sahu P. K., Manna K. , Shah N. , Chattopadhyay S. By Journal of Systems Architecture 60 562-578 (2014)
Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip Sahu P. K., Manna K. , Shah N. , Chattopadhyay S. By Journal of Systems Architecture 60 562-578 (2014)
Multi-application network-on-chip design using global mapping and local reconfiguration Soumya J., Sharma A. , Chattopadhyay S. By ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 7- (2014)
Framework for multiple-fault diagnosis based on multiple fault simulation using particle swarm optimization Kundu S., Jha A. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 696-700 (2014)
Multi-application network-on-chip design using global mapping and local reconfiguration Soumya J., Sharma A. , Chattopadhyay S. By ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 7- (2014)
Framework for multiple-fault diagnosis based on multiple fault simulation using particle swarm optimization Kundu S., Jha A. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 696-700 (2014)
Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization Sahu P. K., Shah T. , Manna K. , Chattopadhyay S. By IEEE transactions on very large scale integration (VLSI) systems 22 300-312 (2014)
Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization Sahu P. K., Shah T. , Manna K. , Chattopadhyay S. By IEEE transactions on very large scale integration (VLSI) systems 22 300-312 (2014)
Application-Specific Network-on-Chip synthesis with flexible router Placement Soumya J., Chattopadhyay S. By Journal of Systems Architecture 59 361-371 (2013)
Application-Specific Network-on-Chip synthesis with flexible router Placement Soumya J., Chattopadhyay S. By Journal of Systems Architecture 59 361-371 (2013)
A survey on application mapping strategies for network-on-chip design Sahu P. K., Chattopadhyay S. By Journal of Systems Architecture 59 60-76 (2013)
A survey on application mapping strategies for network-on-chip design Sahu P. K., Chattopadhyay S. By Journal of Systems Architecture 59 60-76 (2013)
A metric for test set characterization and customization toward fault diagnosis Kundu S., Pal S. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2013)
A metric for test set characterization and customization toward fault diagnosis Kundu S., Pal S. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2013)
Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing Kumar S. K., Kundu S. , Chattopadhyay S. By Integration, the VLSI Journal 45 211-221 (2012)
Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing Kumar S. K., Kundu S. , Chattopadhyay S. By Integration, the VLSI Journal 45 211-221 (2012)
Multiplexer-based multi-level circuit synthesis with area-power trade-off Pradhan S. N., Chattopadhyay S. By Journal of Circuits, Systems, and Computers 21 1250-1265 (2012)
Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router Kundu S., Soumya J. , Chattopadhyay S. By Microprocessors and Microsystems 36 471-488 (2012)
Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router Kundu S., Soumya J. , Chattopadhyay S. By Microprocessors and Microsystems 36 471-488 (2012)
Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique Mitra A., Chattopadhyay S. By Chattopadhyay IET Computers & Digital Techniques 6 353-361 (2012)
Multiplexer-based multi-level circuit synthesis with area-power trade-off Pradhan S. N., Chattopadhyay S. By Journal of Circuits, Systems, and Computers 21 1250-1265 (2012)
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison Manna K., Chattopadhyay S. , Sengupta I. By International Journal of High Performance Systems Architecture 4 25-37 (2012)
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison Manna K., Chattopadhyay S. , Sengupta I. By International Journal of High Performance Systems Architecture 4 25-37 (2012)
Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique Mitra A., Chattopadhyay S. By Chattopadhyay IET Computers & Digital Techniques 6 353-361 (2012)
Low power finite state machine synthesis using power-gating Pradhan S. N., Kumar M. T., Chattopadhyay S. By Integration, the VLSI Journal 44 175-184 (2011)
AND-OR-XOR Network Synthesis with Area-Power trade-off Pradhan S. N., Kumar M. T., Chattopadhyay S. By Journal of Circuits, Systems, and Computers 20 1019-1035 (2011)
AND-OR-XOR Network Synthesis with Area-Power trade-off Pradhan S. N., Kumar M. T., Chattopadhyay S. By Journal of Circuits, Systems, and Computers 20 1019-1035 (2011)
Low power finite state machine synthesis using power-gating Pradhan S. N., Kumar M. T., Chattopadhyay S. By Integration, the VLSI Journal 44 175-184 (2011)
Genetic algorithm-based FSM synthesis with area-power trade-offs Chaudhury S., Sistla K. T., Chattopadhyay S. By INTEGRATION, the VLSI journal 42 376-384 (2009)
Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs Giri C., Rao B. M., Chattopadhyay S. By International Journal of Electronics 96 935-942 (2009)
State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis Chaudhury S., Rao J. S., Chattopadhyay S. By Chattopadhyay Journal of Low Power Electronics 5 464-473 (2009)
Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs Giri C., Rao B. M., Chattopadhyay S. By International Journal of Electronics 96 935-942 (2009)
State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis Chaudhury S., Rao J. S., Chattopadhyay S. By Chattopadhyay Journal of Low Power Electronics 5 464-473 (2009)
Genetic algorithm-based FSM synthesis with area-power trade-offs Chaudhury S., Sistla K. T., Chattopadhyay S. By INTEGRATION, the VLSI journal 42 376-384 (2009)
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology Kundu S., Chattopadhyay S. By International Journal of High Performance Systems Architecture 1 163-182 (2008)
A genetic algorithm based approach for system-on-chip test scheduling using dual speed TAM with power constraint Giri C., Kumar D. , Tipparthi R. , Chattopadhyay S. By WSEAS Transactions on circuits and systems 7 416-427 (2008)
A genetic algorithm based approach for system-on-chip test scheduling using dual speed TAM with power constraint Giri C., Kumar D. , Tipparthi R. , Chattopadhyay S. By WSEAS Transactions on circuits and systems 7 416-427 (2008)
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology Kundu S., Chattopadhyay S. By International Journal of High Performance Systems Architecture 1 163-182 (2008)
Area conscious state assignment with flip-flop and output polarity selection for finite state machine synthesis - a genetic algorithm approach Chattopadhyay S. By The Computer Journal 48 443-450 (2005)
Area conscious state assignment with flip-flop and output polarity selection for finite state machine synthesis - a genetic algorithm approach Chattopadhyay S. By The Computer Journal 48 443-450 (2005)
Finite state machine state assignment targeting low power consumption Chattopadhyay S., Reddy P. N. By IEE Proceedings-Computers and Digital Techniques 151 61-70 (2004)
Finite state machine state assignment targeting low power consumption Chattopadhyay S., Reddy P. N. By IEE Proceedings-Computers and Digital Techniques 151 61-70 (2004)
Low power state assignment and flipflop selection for finite state machine synthesis - a genetic algorithmic approach Chattopadhyay S. By IEE Proceedings-Computers and Digital Techniques 148 147-151 (2001)
Low power state assignment and flipflop selection for finite state machine synthesis - a genetic algorithmic approach Chattopadhyay S. By IEE Proceedings-Computers and Digital Techniques 148 147-151 (2001)
Theory and application of non-group cellular automata for message authentication Dasgupta P., Chattopadhyay S. , Sengupta I. By Journal of Systems Architecture 47 383-404 (2001)
Theory and application of non-group cellular automata for message authentication Dasgupta P., Chattopadhyay S. , Sengupta I. By Journal of Systems Architecture 47 383-404 (2001)
Cellular automata-based recursive pseudoexhaustive test pattern generator Dasgupta P., Chattopadhyay S. , Chaudhuri P. P., Sengupta I. By IEEE Transactions on Computers 50 177-185 (2001)
Cellular automata-based recursive pseudoexhaustive test pattern generator Dasgupta P., Chattopadhyay S. , Chaudhuri P. P., Sengupta I. By IEEE Transactions on Computers 50 177-185 (2001)
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier Chattopadhyay S., Sengupta S. , Adhikari S. , Pal M. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 724-735 (2000)
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier Chattopadhyay S., Sengupta S. , Adhikari S. , Pal M. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 724-735 (2000)
Cellular-automata-array-based diagnosis of board level faults Chattopadhyay S., Chowdhury D. R., Bhattacharjee S. , Chaudhuri P. P. By IEEE transactions on computers 47 817-828 (1998)
Cellular-automata-array-based diagnosis of board level faults Chattopadhyay S., Chowdhury D. R., Bhattacharjee S. , Chaudhuri P. P. By IEEE transactions on computers 47 817-828 (1998)
KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer Chattopadhyay S., Roy S. , Chaudhuri P. P. By IEEE transactions on computer-aided design of integrated circuits and systems - (1997)
KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer Chattopadhyay S., Roy S. , Chaudhuri P. P. By IEEE transactions on computer-aided design of integrated circuits and systems - (1997)
Synthesis of highly testable fixed-polarity AND-XOR canonical networks-A genetic algorithm-based approach Chattopadhyay S., Roy S. , Chaudhuri P. P. By IEEE transactions on computers 45 487-490 (1996)
Synthesis of highly testable fixed-polarity AND-XOR canonical networks-A genetic algorithm-based approach Chattopadhyay S., Roy S. , Chaudhuri P. P. By IEEE transactions on computers 45 487-490 (1996)
CAA decoder for cellular automata based byte error correcting code Sasidhar K., Chattopadhyay S. , Chaudhuri P. P. By IEEE transactions on computers 45 1003-1016 (1996)
CAA decoder for cellular automata based byte error correcting code Sasidhar K., Chattopadhyay S. , Chaudhuri P. P. By IEEE transactions on computers 45 1003-1016 (1996)
KGPMAP: library-based technology-mapping technique for antifuse based FPGAs Chattopadhyay S., Roy S. , Chaudhuri P. P. By IEE Proceedings-Computers and Digital Techniques 141 361-368 (1994)
KGPMAP: library-based technology-mapping technique for antifuse based FPGAs Chattopadhyay S., Roy S. , Chaudhuri P. P. By IEE Proceedings-Computers and Digital Techniques 141 361-368 (1994)

Conferences

Energy-Efficient and Secure Network-on-Chip Architectures for DSP Applications N. P., Chattopadhyay S. , Chakrabarti I. By 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID) 1-6 (2019)
Energy-Efficient and Secure Network-on-Chip Architectures for DSP Applications N. P., Chattopadhyay S. , Chakrabarti I. By 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID) 1-6 (2019)
A New Logic Encryption Strategy Ensuring Key Interdependency Karmakar R., Prasad N. , Chattopadhyay S. , Kapur R. , Sengupta I. By VLSI Design 429-434 (2017)
A New Logic Encryption Strategy Ensuring Key Interdependency Karmakar R., Prasad N. , Chattopadhyay S. , Kapur R. , Sengupta I. By VLSI Design 429-434 (2017)
Runtime mitigation of illegal packet request attacks in Networks-on-Chip Prasad N., Karmakar R. , Chattopadhyay S. , Chakrabarti I. By ISCAS 1-4 (2017)
Runtime mitigation of illegal packet request attacks in Networks-on-Chip Prasad N., Karmakar R. , Chattopadhyay S. , Chakrabarti I. By ISCAS 1-4 (2017)
Optimization of the IEEE 1687 access network for hybrid access schedules Nuthakki S. S., Karmakar R. , Chattopadhyay S. , Chakrabarty K. By VTS 1-6 (2016)
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip Manna K., Chattopadhyay S. , Sengupta I. By ISVLSI 583-586 (2016)
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs Manna K., Sagar C. S., Chattopadhyay S. , Sengupta I. By ISVLSI 529-534 (2016)
Thermal-Safe Schedule Generation for System-on-Chip Testing Karmakar R., Chattopadhyay S. By VLSI Design 475-480 (2016)
Optimization of the IEEE 1687 access network for hybrid access schedules Nuthakki S. S., Karmakar R. , Chattopadhyay S. , Chakrabarty K. By VTS 1-6 (2016)
A strategy for fault tolerant reconfigurable Network-on-Chip design Chatterjee N., Mukherjee P. , Chattopadhyay S. By VDAT 1-2 (2016)
A strategy for fault tolerant reconfigurable Network-on-Chip design Chatterjee N., Mukherjee P. , Chattopadhyay S. By VDAT 1-2 (2016)
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip Manna K., Chattopadhyay S. , Sengupta I. By ISVLSI 583-586 (2016)
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs Manna K., Sagar C. S., Chattopadhyay S. , Sengupta I. By ISVLSI 529-534 (2016)
Thermal-Safe Schedule Generation for System-on-Chip Testing Karmakar R., Chattopadhyay S. By VLSI Design 475-480 (2016)
An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets Nuthakki S. S., Chattopadhyay S. By ATS 151-156 (2015)
Fault tolerant mesh based Network-on-Chip architecture Chatterjee N., Chattopadhyay S. By ISCAS 417-420 (2015)
GA based diagnostic test pattern generation for transition faults Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R. By VDAT 1-6 (2015)
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints Karmakar R., Agarwal A. , Chattopadhyay S. By ATS 73-78 (2015)
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach Karmakar R., Agarwal A. , Chattopadhyay S. By VTS 1-6 (2015)
Test set customization for improved fault diagnosis without sacrificing coverage Nuthakki S. S., Chattopadhyay S. , Chakraborty M. By ISCAS 1574-1577 (2015)
Thermal-Aware Test Data Compression Using Dictionary Based Coding Karmakar R., Chattopadhyay S. By VLSI Design 53-58 (2015)
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning Manna K., Teja V. S., Chattopadhyay S. , Sengupta I. By ISVLSI 392-397 (2015)
A constructive heuristic for application mapping onto an express channel based Network-on-Chip De'souza S., Soumya J. , Chattopadhyay S. By VDAT 1-6 (2015)
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints Karmakar R., Agarwal A. , Chattopadhyay S. By ATS 73-78 (2015)
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach Karmakar R., Agarwal A. , Chattopadhyay S. By VTS 1-6 (2015)
Test set customization for improved fault diagnosis without sacrificing coverage Nuthakki S. S., Chattopadhyay S. , Chakraborty M. By ISCAS 1574-1577 (2015)
Thermal-Aware Test Data Compression Using Dictionary Based Coding Karmakar R., Chattopadhyay S. By VLSI Design 53-58 (2015)
A hardware based low temperature solution for VLSI testing using decompressor side masking Dutta A., Kundu S. , Chattopadhyay S. , Das B. K. By ISCAS 637-640 (2015)
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning Manna K., Teja V. S., Chattopadhyay S. , Sengupta I. By ISVLSI 392-397 (2015)
A constructive heuristic for application mapping onto an express channel based Network-on-Chip De'souza S., Soumya J. , Chattopadhyay S. By VDAT 1-6 (2015)
Particle swarm optimization approach for low temperature BIST Dutta A., Chattopadhyay S. By VDAT 1-6 (2015)
A hardware based low temperature solution for VLSI testing using decompressor side masking Dutta A., Kundu S. , Chattopadhyay S. , Das B. K. By ISCAS 637-640 (2015)
Power- and thermal-aware testing of VLSI circuits and systems Chattopadhyay S. By VDAT 1-1 (2015)
An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets Nuthakki S. S., Chattopadhyay S. By ATS 151-156 (2015)
Fault tolerant mesh based Network-on-Chip architecture Chatterjee N., Chattopadhyay S. By ISCAS 417-420 (2015)
Particle swarm optimization approach for low temperature BIST Dutta A., Chattopadhyay S. By VDAT 1-6 (2015)
Power- and thermal-aware testing of VLSI circuits and systems Chattopadhyay S. By VDAT 1-1 (2015)
GA based diagnostic test pattern generation for transition faults Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R. By VDAT 1-6 (2015)

Book

Thermal-Aware Testing of Digital VLSI Circuits and Systems Chattopadhyay S. By 1-138 (2018)
Thermal-Aware Testing of Digital VLSI Circuits and Systems Chattopadhyay S. By 1-138 (2018)
Network-on-Chip: The Next Generation System-on-Chip Integration Kundu S., Chattopadhyay S. By 1-388 (2014)
Network-on-Chip: The Next Generation System-on-Chip Integration Kundu S., Chattopadhyay S. By 1-388 (2014)
Embedded System Design Chattopadhyay S. By 1-226 (2013)
Embedded System Design Chattopadhyay S. By 1-226 (2013)
Compiler Design - Chinese Edition Chattopadhyay S. By 1-196 (2009)
Compiler Design - Chinese Edition Chattopadhyay S. By 1-196 (2009)
System Software Chattopadhyay S. By 1-195 (2007)
System Software Chattopadhyay S. By 1-195 (2007)
Compiler Design Chattopadhyay S. By 1-225 (2006)
Compiler Design Chattopadhyay S. By 1-225 (2006)
Additive Cellular Automata Theory and Applications (Volume I) Chaudhuri P. P., Chowdhury D. R., Nandi S. , Chattopadhyay S. By 1-340 (1997)
Additive Cellular Automata Theory and Applications (Volume I) Chaudhuri P. P., Chowdhury D. R., Nandi S. , Chattopadhyay S. By 1-340 (1997)

Electronics and Electrical Communication Engg.

Faculty

Research Areas

Principal Investigator

Co-Principal Investigator

Ph. D. Students

Amandeep Singh