Indian Institute of Technology Kharagpur

Swapna Banerjee

Ph.D.(IIT Kharagpur)

Professor, Electronics & Electrical Communication Engineering
Head of the Department, Electronics & Electrical Communication Engineering

Swapna Banerjee joined the Institute in 1981

Contact Addresses

Residence	B-165, IIT Campus, Kharagpur 721302
Phone (office)	+91 - 3222 - 283500
Phone (residence)	+91 - 3222 - 283405 (IIT Phone) +91 - 3222 - 277207 (Private Phone)
email	swapna @ ece.iitkgp.ernet.in
More Information	http://www.ecdept.iitkgp.ernet.in/index.php/home/faculty/swapna

Research Areas

VLSI based embedded system design for signal/image processing
Biomedical Instrumentation
Device modeling
Low power circuits
Mixed-signal design

Fellow

Institute of Engineers

Member of Professional Bodies

Senior Member : IEEE
Presidents nominee : NIT Council

Current Sponsored Projects

Project Title : Special Manpower Development Programme for VLSI Design & related Software
Principal Investigator : Swapna Banerjee
Co-Principal-Investigators : Chitta Ranjan Mandal
Sponsor : Ministry of Communication and Information Technology, New Delhi
Project Title : Design of radiation hardened data converters
Principal Investigator : Swapna Banerjee
Co-Principal-Investigators : Subrata Sanyal
Sponsor : ISRO, STC, I.I.T Kharagpur Cell.
Project Title : Design & development of non-invasive blood glucose measuring system
Principal Investigator : Swapna Banerjee
Co-Principal-Investigators : A.S. Dhar
Sponsor : Department of Information Technology
Project Title : An embedded low cost portable CW Doppler Ultrasonography System
Principal Investigator : Swapna Banerjee
Co-Principal-Investigators : A.S. Dhar
Sponsor : DST, New Delhi.
Project Title : Non-invasive blood glucose measurement system: Prototype development, Evaluation & Testing
Principal Investigator : Swapna Banerjee
Co-Principal-Investigators : Anindya Sundar Dhar
Sponsor : ICMR, New Delhi

Publications: 2012 - 2013

Area Efficient, High Speed EBCOT Architecture for Digital Cinema by Kishor Sarawadekar, Student Member, Swapna Banerjee,Senior Member ISRN Signal Processing, Vol. 2012, 9 pages (2012)
An FPGA-based architecture of DSC_SRI units specially for blind ultrasound systems by Rakesh Biswas, Kishor Sarawadekar,Srinivas Varna,Swapna Banerjee, J Real-Time Image Proc, DOI 10.1007/s11554-0 (2012)

Publications: 2011 - 2012

An efficient pass-parallel architecture for embedded block coder in JPEG 2000 by K. Sarawadekar and S. Banerjee IEEE Transactions Circuits and Systems for Video Technology, Vol. 21,pp.825- 836 (2011)
An Unified Architecture for Affine Transformations of 2D Images for Real Time Applications by P.K. Biswal and S. Banerjee International Journal of Imaging and Robotics, Vol. 5,pp. 28-42 (2011)
Symbolic noise modeling, analysis and optimization of a CMOS input buffer by Santosh Kumar Patnaik and Swapna Banerjee International journal of Analog Integrated Circuits and Signal Processing (ISSN 0925-1030), (2011)
Simulation of digital scan conversion for ultrasound systems using a digital signal processor by Deep Bera, Leeladhar Agarwal and Swapna Banerjee The journal of Ultrasound, Vol. 19,pp.140-150 (2011)
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000 by Kishor Sarawadekar and Swapna Banerjee INTEGRATION, the VLSI journal, Vol. 45,pp. 1-8 (2012)
VLSI-DSP Based Real Time Solution of DSC-SRI for an Ultrasound System by K. Sarawadekar, D. Bera, H.B. Indana, S. Banerjee Microprocessors and Microsystems, Vol. 36, pp. 1–12 (2012)
Parallel architecture for accelerating affine transform in high-speed imaging systems by Pradyut Kumar Biswal, Pulak Mondal and Swapna Banerjee Real-Time Image Processing, Vol. 6 (2011)
Linearity Enhancement of 0.18 μm Transconductor using Active Attenuation Technique by Vijaya Bhadauria, Krishna Kant, Swapna Banerjee Canadian Journal on Electrical and Electronics Engineering, Vol. 2,pp. 598-601 (2011)
Design and Analysis of A Power Efficient Linearly Tunable Cross – Coupled Transconductor having Separate Bias Control by Vijaya Bhadauria, Krishna Kant, Swapna Banerjee Circuit and System of Scientific research, Vol.3 (2012)

Publications: 2010 - 2011

An FFT based Fast Reconstruction Algorithm for 3D Computed Tomography by Abhishek Mitra and Swapna Banerjee International Journal of Tomography & Statistics, Vol. 15, pp. 70-77 (2010)
An Efficient Architecture for 3-D Discrete Wavelet Transform by Anirban Das, Anindya Hazra and Swapna Banerjee IEEE Transactions on Circuits and Systems for video technology, Vol. 20, pp. 286-296 (2010)
Architectural Design and FPGA Implementation of Radix-4 CORDIC Processor by Kaushik Bhattacharyya, Rakesh Biswas, Anindya S. Dhar and Swapna Banerjee Microprocessors and Microsystems (MICPRO, Elsevier) Embedded Hardware Design, Vol. 34, pp.96-101 (2010)
An efficient pass-parallel architecture for embedded block coder in JPEG 2000 (Accepted) by K. Sarawadekar and S. Banerjee IEEE Transactions on Circuits and Systems for Video Technology, (0)

Publications: 2009 - 2010

An Efficient Architecture for 3-D Discrete Wavelet Transform, by Anirban Das, Anindya Hazra and Swapna Banerjee IEEE Transactions on Circuits and Systems for video technology, 20, pp. 286-296 (2010)
An FFT based Fast Reconstruction Algorithm for 3D Computed Tomography, by Abhishek Mitra and Swapna Banerjee International Journal of Tomography & Statistics, 15, pp. 70-77 (2010)
Architectural Design and FPGA Implementation of Radix-4 CORDIC Processor (Accepted), by Kaushik Bhattacharyya, Rakesh Biswas, Anindya S. Dhar and Swapna Banerjee. Microprocessors and Microsystems(MICPRO, Elsevier) Embedded Hardware Design, (2010)
Architectural designof a Radix-4 CORDIC based Radix-4 IFFT algorithm and its FPGA implementation by K.Bhattacharya, A.Hazra, I.Hatai and S.Banerjee Int. J. Signal and Imaging Systems Engineering, accepted (2010)

Publications: 2007 - 2008

Power Delay Optimization of Nanoscale CMOS Inverter Using Geometric Programming by Manisha Pattanaik, Swapna Banerjee and Bikram K. Bahinipati WSEAS Transactions on Circuits and Systems, Issue 4, Vol. 5 (2006)

Publications: 2006 - 2007

A New Approach to Analyze a Nanoscale CMOS Buffer by Manisha Pattanaik and Swapna Banerjee WSEAS Transactions on Circuits and Systems, Issue 2, Vol. 5 (2006)

Publications: 2005 - 2006

Modified Virtually Scalling-Free Adaptive CORDIC Rotator Algorithm and Architecture by Swapna Banerjee, Koushik Maharatna, Eckhard Grass, Milos Krstic and Alfonso Troya IEEE Transaction on circuits and systems for video technology, Vol.15, pp.1463-1474 (2005)
Performance analysis of different wavelet feature vectors in quantification of oral precancers condition by Anirban Mukherjee, Ranjan Rashmi Paul, Keya Chaudhuri, Jyotirmoy Chatterjee, Mousumi Pal, Provas Banerjee, Kanchan Mukherjee, Swapna Banerjee, Pranab K. Dutta ELSEVIER, (2005)
A New Approach to Analyze a Nanoscale CMOS Buffer by Manisha Pattanaik and Swapna Banerjee WSEAS Transactions on Circuits and Systems, Vol. 5, pp 190-195 (2006)
Power Delay Optimization of Nanoscale CMOS Inverter Using Geometric Programming by Manisha Pattanaik, Swapna Banerjee and Bikram K. Bahinipati WSEAS Transactions on Circuits and Systems, Vol. 5 pp. 536-541 (2006)

Some Earlier Publications

A United CORDIC- based Chip to Realize DFT / DHT / DCT / DST by Pal & Swapna Banerjee IEE Proc. on Computer and Digital Techniques, (2002)
FPGA Realization of a CORDIC Based FFT processor for biomedical signal processing by Banerjee, A. S. Dhar & Swapna Banerjee Microprocessor & Microsystems, 25/3 PP 131-142 (2001)
A VLSI array Architecture for Realization of DFT by S. Dhar, K. Maharatna & S. Banerjee DHT, DCT and ()
A VLSI Array Architecture for Hough Transform by K. Maharatna & S. Banerjee Pattern Recognition, 34 PP 1503-1512 (2001)

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