
Area of Research: Data Mining
Area of Research: Computer Networking
Area of Research: Academic Information Systems
Area of Research: Education Technology
Area of Research: Data analytics
Area of Research: Applied AI
Area of Research: Applied machine learning
Area of Research: Analog VLSI Design Methodology
Thesis Title: Design for Manufacturability aware Early Global Routing
Area of Research: Networks
Thesis Title: Sustainable and Energy-Efficient Connectivity for IoT Networks
Area of Research: Computation modelling of physical systems
Thesis Title: Computational Methods for Modelling and Analysis of Thyrotropic Regulation Pathway
Area of Research: Applications of Networks
Thesis Title: Towards Scalable SDN: Enhancement in Data and Control Planes
Area of Research: Networking
Thesis Title: Construction and Maintenance of Connected Dominating Set as Virtual Backbone in Wireless Network
Area of Research: Eductional Technology
Thesis Title: Application of Equivalence Checking for Evaluation of Students'' Programming Assignments
Area of Research: Formal Verification
Thesis Title: Translation validation of optimizing transformations of programs using equivalence checking
Area of Research: Computation modelling of physical systems
Thesis Title: Application of Computational Modelling towards Digital Twinning for Human Physiological and Biochemical Processes
Area of Research: formal verification
Thesis Title: Path Based Equivalence Checking of Petri Net Representation of Programs for Translation Validation
Area of Research: Railway Signal Interlocking
Thesis Title: Techniques and Tools for Railway Signal Interlocking
Area of Research: IT for e-learning
Thesis Title: Techniques and Algorithms for the Design and Development of a Virtual Laboratory to Support Logic Design and Computer Organization
Area of Research: VLSI Design
Thesis Title: Design of Power Attack Resistant Circuits for Cryptography
Area of Research: Image processing and machine learning for railway applications
Thesis Title: Extracting Tracks and Points from Railway Yard ESP Images
Area of Research: Signalling system design and validation
Thesis Title: SigDATE$^\textregistered$$\colon$ A Computational Approach to Automated Signalling Design for Electronic Interlocking Systems
Area of Research: Formal modelling and analysis
Thesis Title: Formal Verification of Application Logic in Railway Signaling and Interlocking Systems
Area of Research: VLSI Design and Education Technology
Thesis Title: Transistor Parameter Determination for Digital Circuits
You are about to leave this site. Continue?