Rajat Subhra Chakraborty


Computer Science and Engineering




  • Associate Dean, Faculty of Engineering and Architecture (FoE&A)

Research Areas

My research interests are in the areas of Hardware Security, Application of Novel Nano-devices to Hardware Security, VLSI Design and Methodologies and Digital Multimedia Security. I am part of the "Secured Embedded Architecture Laboratory" (SEAL), where we focus on applied security research. For more details about my professional activities and publications, please refer to https://sites.google.com/site/rschakraborty/.

My Google Scholar profile: https://scholar.google.com/citations?user=ITIg9kkAAAAJ&hl=en&oi=ao

My DBLP Profile: https://dblp.org/pid/05/1579.html
  • Multi-level Inline Data Deduplication R. S. Chakraborty and B. K. Diddi By U.S. Patent No. 9,311,323 - (2016)
  • ORACALL: An Oracle-Based Attack on Cellular Automata Guided Logic Locking Saha A., Banerjee H., Chakraborty R.S., Mukhopadhyay D. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40 2445-2454 (2021)
  • Protection of Intellectual Property Cores Through a Design Flow R. S. Chakraborty, S. Narasimhan and S. Bhunia By U.S. patent No. 8,402,401 - (2014)
  • System and Method for Dynamic Partial Reconfiguration of Circuits Mapped or Configured on FPGA Platform (Indian patent No. 417967) Johnson A., Chakraborty R. S., Mukhopadhyay D. , Irani C. By - (2023)
  • A Method and System for Evaluation of Reversible Watermarking of Digital Images and Audio (Indian Patent. No. 405072) Naskar R., Sarkar B. , Chakraborty R. S. By - (2022)
  • Attacks on Recent DNN IP Protection Techniques and Their Mitigation Mukherjee R., Chakraborty R. S. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (Accepted/In-Press)
  • Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators Mukherjee R., Chakraborty R.S. By IEEE Embedded Systems Letters 14 131-134 (2022)
  • 3PAA: A Private PUF Protocol for Anonymous Authentication Chaterjee U., Mukhopadhyay D., Chakraborty R.S. By IEEE Transactions on Information Forensics and Security 16 756-769 (2021)
  • A Computationally Efficient Tensor Regression Network based Modeling Attack on XOR Arbiter PUF and its Variants Santikellur P., Chakraborty R.S. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40 1197-1206 (2021)

Principal Investigator

  • Digital Image Forensics in the Context of a Connected India Algorithms and Implementation Department of Science and Technology (DST)
  • Security Course Development for Intel (R) Unnati Program INTEL TECHNOLOGY INDIA PRIVATE LIMITED

Co-Principal Investigator

  • Cyber Security of Power Systems through Design-for Prevention, Real-time Detection and Effective Intervention Central Power Research Institute
  • Secure Resource-Constrained Communication Framework for Tactical Networks Using Physically Unclonable Functions (SeRFPUF) Directorate of Futuristic Technology Management (DFTM), Defence Research and Development Organisation, Ministry of Defence

Ph. D. Students

Akashdeep Saha

Area of Research: Hardware Security

B V Sreekanth

Area of Research: Hardware Security Issues in Network Security

Kuheli Pratihar

Area of Research: Hardware Security

Rijoy Mukherjee

Area of Research: Hardware Security

Sivappriya M

Area of Research: Hardware Security

Souvik Sonar

Area of Research: Cryptography

MS Students

Pallavi Anand

Area of Research: Machine Learning aided Hardware Security

Sneha Swaroopa

Area of Research: Hardware Security

Sumitava Biswas

Area of Research: Blockchain Security