My research is focussed primarily in the area of designing various high speed parallel and pipelined VLSI architectures. Most of the works are related to the design and development of CORDIC based high throughput digital VLSI architectures for signal processing applications, ranging from those in the image processing, communication, to those in the biomedical domain. CORDIC provides an efficient and economic means of implementing transcendental functions in digital hardware that uses binary arithmetic. The developed architectures are mainly targeted to be deployed in real-time environments. One of the significant contributions is in the reduction of the latency of such pipelined structures. Though mostly the architectures designed are working in the digital domain, another significant research direction is towards the design of sampled analog architectures that can implement any digital signal processing algorithm much economically with unquantized samples using analog techniques, thereby having the best of both the analog and the digital worlds. This technique is capable of providing cost-effective solutions for the signal processing applications where a moderate accuracy of computation is sufficient. In a nutshell, my research area is mostly in the field of the design and development of high speed low latency VLSI architecture for real time signal processing applications.
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Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling by Dhar A. S., Patra R. K. Circuits, Systems, and Signal Processing 42 7275-7296 (2023)
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A Novel Nested Array for Real-Valued Sources Exploiting Array Motion by Patra R.K., Dhar A.S. IEEE Signal Processing Letters 28 1375-1379 (2021)
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An Improved CACIS Configuration for DOA Estimation with Enhanced Degrees of Freedom by Patra R.K., Dhar A.S. Circuits, Systems, and Signal Processing 42 1860-1872 (2023)
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A Novel Translated Coprime Array Configuration for Moving Platform in Direction-of-Arrival Estimation by Patra R.K., Dhar A.S. Circuits, Systems, and Signal Processing 42 2494-2505 (2023)
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Optimal Coprime Array: Properties, Optimization, and k-times extension by Patra R.K., Dhar A.S. Circuits, Systems, and Signal Processing - (2023)
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ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design by Roy A.S., Agrawal H., Dhar A.S. IEEE Transactions on Emerging Topics in Computing 10 2072-2078 (2022)
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A new fraction phase based low energy frequency calibration architecture along with an ultra low power VCO design by Ghosh A., Dhar A.S., Halder A. Analog Integrated Circuits and Signal Processing 111 117-135 (2022)
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FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion by Palchaudhuri A., Anand D., Dhar A.S. Journal of Parallel and Distributed Computing 167 50-63 (2022)
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A Novel k-times Extended Coprime Array for DOA Estimation with Increased Degrees of Freedom by Patra R.K., Dhar A.S. IEEE Signal Processing Letters 29 1402-1406 (2022)
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Novel Moving Coprime Array Configurations for Real-Valued Sources by Patra R.K., Dhar A.S. IEEE Signal Processing Letters 29 657-661 (2022)
- Co-Principal Investigator
Ph. D. Students
Kaushik Khatua
Area of Research: Machine learning techniques for VLSI design
Sahadeb Santra
Area of Research: VLSI Architecture Design
